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[68.147.8.254]) by smtp.gmail.com with ESMTPSA id v204sm2195864pfc.10.2020.09.28.08.58.10 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 28 Sep 2020 08:58:11 -0700 (PDT) Date: Mon, 28 Sep 2020 09:58:09 -0600 From: Mathieu Poirier To: Sai Prakash Ranjan Subject: Re: [PATCHv2 2/2] coresight: etm4x: Fix save and restore of TRCVMIDCCTLR1 register Message-ID: <20200928155809.GA16823@xps15> References: <011321608e06db0a2797d3a0418b81c75438c571.1601292571.git.saiprakash.ranjan@codeaurora.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <011321608e06db0a2797d3a0418b81c75438c571.1601292571.git.saiprakash.ranjan@codeaurora.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_115815_161111_1A02C77D X-CRM114-Status: GOOD ( 22.03 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , alexander.shishkin@linux.intel.com, linux-arm-msm@vger.kernel.org, coresight@lists.linaro.org, linux-kernel@vger.kernel.org, Stephen Boyd , peterz@infradead.org, leo.yan@linaro.org, linux-arm-kernel@lists.infradead.org, Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 28, 2020 at 05:07:09PM +0530, Sai Prakash Ranjan wrote: > In commit f188b5e76aae ("coresight: etm4x: Save/restore state > across CPU low power states"), mistakenly TRCVMIDCCTLR1 register > value was saved in trcvmidcctlr0 state variable which is used to > store TRCVMIDCCTLR0 register value in etm4x_cpu_save() and then > same value is written back to both TRCVMIDCCTLR0 and TRCVMIDCCTLR1 > in etm4x_cpu_restore(). There is already a trcvmidcctlr1 state > variable available for TRCVMIDCCTLR1, so use it. > > Fixes: f188b5e76aae ("coresight: etm4x: Save/restore state across CPU low power states") > Reviewed-by: Suzuki K Poulose > Signed-off-by: Sai Prakash Ranjan I am applying your patch (this one only) - hopefully it can go in the 5.10 cycle. Thanks, Mathieu > --- > drivers/hwtracing/coresight/coresight-etm4x-core.c | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c > index de76d57850bc..abd706b216ac 100644 > --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c > +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c > @@ -1243,7 +1243,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata) > state->trccidcctlr1 = readl(drvdata->base + TRCCIDCCTLR1); > > state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR0); > - state->trcvmidcctlr0 = readl(drvdata->base + TRCVMIDCCTLR1); > + state->trcvmidcctlr1 = readl(drvdata->base + TRCVMIDCCTLR1); > > state->trcclaimset = readl(drvdata->base + TRCCLAIMCLR); > > @@ -1353,7 +1353,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata) > writel_relaxed(state->trccidcctlr1, drvdata->base + TRCCIDCCTLR1); > > writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR0); > - writel_relaxed(state->trcvmidcctlr0, drvdata->base + TRCVMIDCCTLR1); > + writel_relaxed(state->trcvmidcctlr1, drvdata->base + TRCVMIDCCTLR1); > > writel_relaxed(state->trcclaimset, drvdata->base + TRCCLAIMSET); > > -- > QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member > of Code Aurora Forum, hosted by The Linux Foundation > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel