From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-12.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DF509C2D0A8 for ; Tue, 29 Sep 2020 02:20:48 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 6497A207C4 for ; Tue, 29 Sep 2020 02:20:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ZJLCacaA"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="G6DxSVm/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 6497A207C4 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=He4ey0QyTsp4gJRETIOE1fd6avhwWm/5k7udJhgBUuI=; b=ZJLCacaAWGcr1xIA49vKYsZID 5+XLDAlLSEcnZwFHkpDVbq3tQoMgNwoq8NmyzdqmId4dkvcLiAfogP3hjZQb9Kjah3LFajiwJZdCx WTcj9K3NXrfW5yL1sQ5gIKJMo9jQRGJYj735UM6c9YYHf+L0D0M3gVjhCmOUNq5YLNvcGk0tCXv3f S3/LKqcbUG2L/sdQL7qEhZ0DtezxYw/DhEWM/W2foBrMmTG4L3Uz9PKllcTpru4vDZnHYm4IiXPEg 2SB0Yrp3t+AhYQrxImBrFe81F1RDPWV/IEN8CpGyUEIcds07vNG/uqLULLJTYlGAg3TaQTvgs3mR/ rvg46+fmg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kN5Ee-0005TX-Ul; Tue, 29 Sep 2020 02:19:20 +0000 Received: from mail-pf1-x441.google.com ([2607:f8b0:4864:20::441]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kN5Eb-0005Sg-Cm for linux-arm-kernel@lists.infradead.org; Tue, 29 Sep 2020 02:19:19 +0000 Received: by mail-pf1-x441.google.com with SMTP id n14so3032010pff.6 for ; Mon, 28 Sep 2020 19:19:13 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:content-transfer-encoding:in-reply-to :user-agent; bh=lQaBqY6VJb803KoPdODFXalC90BAvQ5GzxBqbcjKhGI=; b=G6DxSVm/SbQWCx780cgVhlI36BjHX00T8Ux2yJWcYGuPet+iV8W9MVWlTf24P/O3TY 9lWt+hloK60tdwarBdh92Uvy9Z771JSlSgnOWaK8yz/7EF9m3k26jHV2s/9FN61UpxUG M7RuXSoIcdnPFSb6f3llxMHVcFuMAJIXqMHgkpVigUURWwuimJHRWY8p1yM4479Xc2t2 tkaparzndyOPPkOFmmkr869mOKaI+Dj7sGRGgtHvrMx1W53xAA32VHD4m3ALCl0OacAY ZxkRuNp9xyD7yexbCl/Z1ZJEI7+idsitJ5REYjxsBjapO9VdRF9jxrM2n7OWqpclirCb 6mXw== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:content-transfer-encoding :in-reply-to:user-agent; bh=lQaBqY6VJb803KoPdODFXalC90BAvQ5GzxBqbcjKhGI=; b=pH4UGKHHnqB/BsXiQFkP72fOdAgijItzFvBiAKP7BUDY4OgFbQ4F39x3oVicN6KTd9 zsdw99Ri7kDn7l0MqS3m1vnRoIxfaGCk9hCgY2DxJ0zvgTHzXwPCfCzJgmaMNVqz8nbh rImuoTMO0ckE0Os8cEsBEwbBfBRqRWYonhFZczQD9TrlLxT/yQxs35DCwvioyHcsAzXO 9RR0OYq0pjPKz8oVNHXYNsxbkznT6e3ZEUSjKCg4lh4PxC72KcPTZYVnidNgDkFEBvAd PxeNSY0RG7NvasSJoIFo1zzrwhd2tW8LO8QfpoBCriZtJKkUStsHBwGX2kMFNuezqEzC jEGA== X-Gm-Message-State: AOAM530ggUnPvqv40Fi+2YqqTQOgCJOS/81n2pKfxznfUn+ggP6AE5yy 60qVqjR+FDYYscMobd8lHMYcFg== X-Google-Smtp-Source: ABdhPJy+XZRr1qGEsTeUZfNqorpd+qntUhC5OUUunPwMUbFsdqpjZijobKbw/vcJWGvPssbbJJnCtg== X-Received: by 2002:a63:490d:: with SMTP id w13mr1505126pga.24.1601345951682; Mon, 28 Sep 2020 19:19:11 -0700 (PDT) Received: from leoy-ThinkPad-X240s ([2600:3c01::f03c:91ff:fe8a:bb03]) by smtp.gmail.com with ESMTPSA id m188sm3126554pfd.56.2020.09.28.19.19.06 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 28 Sep 2020 19:19:10 -0700 (PDT) Date: Tue, 29 Sep 2020 10:19:02 +0800 From: Leo Yan To: Dave Martin Subject: Re: [PATCH 5/5] perf: arm_spe: Decode SVE events Message-ID: <20200929021902.GA16749@leoy-ThinkPad-X240s> References: <20200922101225.183554-1-andre.przywara@arm.com> <20200922101225.183554-6-andre.przywara@arm.com> <20200928132114.GF6642@arm.com> <8efd63eb-5ae7-0f9a-6c37-ef5e68af4e6c@arm.com> <20200928144755.GI6642@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200928144755.GI6642@arm.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20200928_221917_707072_D58B8778 X-CRM114-Status: GOOD ( 56.74 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Al Grant , Will Deacon , Suzuki K Poulose , Peter Zijlstra , =?iso-8859-1?Q?Andr=E9?= Przywara , Jiri Olsa , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Alexander Shishkin , Ingo Molnar , James Clark , Catalin Marinas , Namhyung Kim , Wei Li , Tan Xiaojun , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Sep 28, 2020 at 03:47:56PM +0100, Dave Martin wrote: > On Mon, Sep 28, 2020 at 02:59:34PM +0100, Andr=E9 Przywara wrote: > > On 28/09/2020 14:21, Dave Martin wrote: > > = > > Hi Dave, > > = > > > On Tue, Sep 22, 2020 at 11:12:25AM +0100, Andre Przywara wrote: > > >> The Scalable Vector Extension (SVE) is an ARMv8 architecture extensi= on > > >> that introduces very long vector operations (up to 2048 bits). > > > = > > > (8192, in fact, though don't expect to see that on real hardware any > > > time soon... qemu and the Arm fast model can do it, though.) > > > = > > >> The SPE profiling feature can tag SVE instructions with additional > > >> properties like predication or the effective vector length. > > >> > > >> Decode the new operation type bits in the SPE decoder to allow the p= erf > > >> tool to correctly report about SVE instructions. > > > = > > > = > > > I don't know anything about SPE, so just commenting on a few minor > > > things that catch my eye here. > > = > > Many thanks for taking a look! > > Please note that I actually missed a prior submission by Wei, so the > > code changes here will end up in: > > https://lore.kernel.org/patchwork/patch/1288413/ > > = > > But your two points below magically apply to his patch as well, so.... > > = > > > = > > >> Signed-off-by: Andre Przywara > > >> --- > > >> .../arm-spe-decoder/arm-spe-pkt-decoder.c | 48 ++++++++++++++++= ++- > > >> 1 file changed, 47 insertions(+), 1 deletion(-) > > >> > > >> diff --git a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c b= /tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > >> index a033f34846a6..f0c369259554 100644 > > >> --- a/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > >> +++ b/tools/perf/util/arm-spe-decoder/arm-spe-pkt-decoder.c > > >> @@ -372,8 +372,35 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *= packet, char *buf, > > >> } > > >> case ARM_SPE_OP_TYPE: > > >> switch (idx) { > > >> - case 0: return snprintf(buf, buf_len, "%s", payload & 0x1 ? > > >> + case 0: { > > >> + size_t blen =3D buf_len; > > >> + > > >> + if ((payload & 0x89) =3D=3D 0x08) { > > >> + ret =3D snprintf(buf, buf_len, "SVE"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > > = > > > (Nit: can ret be < 0 ? I've never been 100% clear on this myself for > > > the s*printf() family -- if this assumption is widespread in perf tool > > > a lready that I guess just go with the flow.) > > = > > Yeah, some parts of the code in here check for -1, actually, but doing > > this on every call to snprintf would push this current code over the > > edge - and I cowardly avoided a refactoring ;-) > > = > > Please note that his is perf userland, and also we are printing constant > > strings here. > > Although admittedly this starts to sounds like an excuse now ... > > = > > > I wonder if this snprintf+increment+decrement sequence could be wrapp= ed > > > up as a helper, rather than having to be repeated all over the place. > > = > > Yes, I was hoping nobody would notice ;-) > = > It's probably not worth losing sleep over. > = > snprintf(3) says, under NOTES: > = > Until glibc 2.0.6, they would return -1 when the output was > truncated. > = > which is probably ancient enough history that we don't care. C11 does > say that a negative return value can happen "if an encoding error > occurred". _Probably_ not a problem if perf tool never calls > setlocale(), but ... I have one patch which tried to fix the snprintf+increment sequence [1], to be honest, the change seems urgly for me. I agree it's better to use a helper to wrap up. [1] https://lore.kernel.org/patchwork/patch/1288410/ > > >> + if (payload & 0x2) > > >> + ret =3D snprintf(buf, buf_len, " FP"); > > >> + else > > >> + ret =3D snprintf(buf, buf_len, " INT"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + if (payload & 0x4) { > > >> + ret =3D snprintf(buf, buf_len, " PRED"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + } > > >> + /* Bits [7..4] encode the vector length */ > > >> + ret =3D snprintf(buf, buf_len, " EVLEN%d", > > >> + 32 << ((payload >> 4) & 0x7)); > > > = > > > Isn't this just extracting 3 bits (0x7)? = > > = > > Ah, right, the comment is wrong. It's actually bits [6:4]. > > = > > > And what unit are we aiming > > > for here: is it the number of bytes per vector, or something else? I= 'm > > > confused by the fact that this will go up in steps of 32, which doesn= 't > > > seem to match up to the architecure. > > = > > So this is how SPE encodes the effective vector length in its payload: > > the format is described in section "D10.2.7 Operation Type packet" in a > > (recent) ARMv8 ARM. I put the above statement in a C file and ran all > > input values through it, it produced the exact *bit* length values as in > > the spec. > > = > > Is there any particular pattern you are concerned about? > > I admit this is somewhat hackish, I can do an extra function to put some > > comments in there. > = > Mostly I'm curious because the encoding doesn't match the SVE > architecture: SVE requires 4 bits to specify the vector length, not 3. > This might have been a deliberate limitation in the SPE spec., but it > raises questions about what should happen when 3 bits is not enough. > = > For SVE, valid vector lengths are 16 bytes * n > or equivalently 128 bits * n), where 1 <=3D n <=3D 16. > = > The code here though cannot print EVLEN16 or EVLEN48 etc. This might > not be a bug, but I'd like to understand where it comes from... In the SPE's spec, the defined values for EVL are: 0b'000 -> EVLEN: 32 bits. 0b'001 -> EVLEN: 64 bits. 0b'010 -> EVLEN: 128 bits. 0b'011 -> EVLEN: 256 bits. 0b'100 -> EVLEN: 512 bits. 0b'101 -> EVLEN: 1024 bits. 0b'110 -> EVLEN: 2048 bits. Note that 0b'111 is reserved. In theory, I think SPE Operation packet can support up to 4196 bits (32 << 7) when the EVL field is 0b'111; but it's impossible to express vector length for 8192 bits as you mentioned. Thanks, Leo > > > I notice that bit 7 has to be zero to get into this if() though. > > > = > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + return buf_len - blen; > > >> + } > > >> + > > >> + return snprintf(buf, buf_len, "%s", payload & 0x1 ? > > >> "COND-SELECT" : "INSN-OTHER"); > > >> + } > > >> case 1: { > > >> size_t blen =3D buf_len; > > >> = > > >> @@ -403,6 +430,25 @@ int arm_spe_pkt_desc(const struct arm_spe_pkt *= packet, char *buf, > > >> ret =3D snprintf(buf, buf_len, " NV-SYSREG"); > > >> buf +=3D ret; > > >> blen -=3D ret; > > >> + } else if ((payload & 0x0a) =3D=3D 0x08) { > > >> + ret =3D snprintf(buf, buf_len, " SVE"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + if (payload & 0x4) { > > >> + ret =3D snprintf(buf, buf_len, " PRED"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + } > > >> + if (payload & 0x80) { > > >> + ret =3D snprintf(buf, buf_len, " SG"); > > >> + buf +=3D ret; > > >> + blen -=3D ret; > > >> + } > > >> + /* Bits [7..4] encode the vector length */ > > >> + ret =3D snprintf(buf, buf_len, " EVLEN%d", > > >> + 32 << ((payload >> 4) & 0x7)); > > > = > > > Same comment as above. Maybe have a common helper for decoding the > > > vector length bits so it can be fixed in a single place? > > = > > Yup. Although I wonder if this is the smallest of the problems with this > > function going forward. > > = > > Cheers, > > Andre > = > Fair enough. > = > Cheers > ---Dave _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel