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Wed, 30 Sep 2020 23:40:10 -0700 (PDT) Received: from kozik-lap ([194.230.155.194]) by smtp.googlemail.com with ESMTPSA id f17sm3200981eds.45.2020.09.30.23.40.09 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Wed, 30 Sep 2020 23:40:09 -0700 (PDT) Date: Thu, 1 Oct 2020 08:40:08 +0200 From: Krzysztof Kozlowski To: Zhen Lei Subject: Re: [PATCH v6 11/17] dt-bindings: arm: hisilicon: convert hisilicon,cpuctrl bindings to json-schema Message-ID: <20201001064008.GE3018@kozik-lap> References: <20200930031712.2365-1-thunder.leizhen@huawei.com> <20200930031712.2365-12-thunder.leizhen@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20200930031712.2365-12-thunder.leizhen@huawei.com> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_024011_964254_7CACEACB X-CRM114-Status: GOOD ( 17.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree , Kefeng Wang , linux-kernel , Wei Xu , Rob Herring , Libin , Jonathan Cameron , linux-arm-kernel Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Sep 30, 2020 at 11:17:06AM +0800, Zhen Lei wrote: > Convert the Hisilicon CPU controller binding to DT schema format using > json-schema. > > Signed-off-by: Zhen Lei > --- > .../bindings/arm/hisilicon/controller/cpuctrl.yaml | 29 ++++++++++++++++++++++ > .../arm/hisilicon/controller/hisilicon,cpuctrl.txt | 8 ------ > 2 files changed, 29 insertions(+), 8 deletions(-) > create mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml > delete mode 100644 Documentation/devicetree/bindings/arm/hisilicon/controller/hisilicon,cpuctrl.txt > > diff --git a/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml > new file mode 100644 > index 000000000000000..f6a314db3a59416 > --- /dev/null > +++ b/Documentation/devicetree/bindings/arm/hisilicon/controller/cpuctrl.yaml > @@ -0,0 +1,29 @@ > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) > +%YAML 1.2 > +--- > +$id: http://devicetree.org/schemas/arm/hisilicon/controller/cpuctrl.yaml# > +$schema: http://devicetree.org/meta-schemas/core.yaml# > + > +title: Hisilicon CPU controller > + > +maintainers: > + - Wei Xu > + > +description: | > + The clock registers and power registers of secondary cores are defined > + in CPU controller, especially in HIX5HD2 SoC. > + > +properties: > + compatible: > + items: > + - const: hisilicon,cpuctrl > + > + reg: > + maxItems: 1 > + > +required: > + - compatible > + - reg Your own DTS file (arch/arm/boot/dts/hisi-x5hd2.dtsi) does not validate against this dtschema. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel