From: Catalin Marinas <catalin.marinas@arm.com>
To: Will Deacon <will@kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD
Date: Thu, 1 Oct 2020 10:52:52 +0100 [thread overview]
Message-ID: <20201001095251.GB21544@gaia> (raw)
In-Reply-To: <20201001093920.18260-1-will@kernel.org>
On Thu, Oct 01, 2020 at 10:39:20AM +0100, Will Deacon wrote:
> TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local
> TLB after setting the bit when detected support for the feature. Although
> this isn't strictly necessary, since we can happily operate with the bit
> effectively clear, the current code uses an ISB in a half-hearted attempt
> to make the change effective, so let's just fix that up.
>
> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Signed-off-by: Will Deacon <will@kernel.org>
> ---
> arch/arm64/kernel/cpufeature.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> index 6424584be01e..29de76046977 100644
> --- a/arch/arm64/kernel/cpufeature.c
> +++ b/arch/arm64/kernel/cpufeature.c
> @@ -1442,7 +1442,7 @@ static inline void __cpu_enable_hw_dbm(void)
> u64 tcr = read_sysreg(tcr_el1) | TCR_HD;
>
> write_sysreg(tcr, tcr_el1);
> - isb();
> + local_flush_tlb_all();
Is the TLBI ordered with the TCR_EL1 write or we need the ISB as well?
--
Catalin
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next prev parent reply other threads:[~2020-10-01 9:54 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-01 9:39 [PATCH] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Will Deacon
2020-10-01 9:52 ` Catalin Marinas [this message]
2020-10-01 10:32 ` Will Deacon
2020-10-01 10:33 ` Mark Rutland
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