From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BE8FBC4727C for ; Thu, 1 Oct 2020 11:23:59 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 70B1E208B6 for ; Thu, 1 Oct 2020 11:23:59 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="LH+VAnXU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 70B1E208B6 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Xg79oNsqKoItg4yIILPx4CvALnsXEsc5bTi7EMLJ/YM=; b=LH+VAnXUfiZsCG/Yy3Yrkixi8 0LSiUDjB78RO+GrSeQzSSCWo//BmD4w8Fy9gn11SG03fUNMLsze15pk8ei0gGAC7iBLvZGgnN1yRc PXaVdosw1ZXyqNnt9CTVqGjo+4ULvGwnUZSqYPvfuT1iW6yHJpwWSR8a7wc0ap4e/Wgume6el2sDR 8yHfh3F1nOR1h4JxSF95Xi7Wa9tAz9Rg662uiEjS2gduvPBhx52GM0UoZttRxRzojHe12kN8jHRhn FgsKc3nr12rWMEWV2VGI5qacfQ5C5ckPBUkr1DcpHPhjla9xyTW6hWkftfog2qMbjnmoBr9qWLAIS V26QsD1hg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNwfI-0003S4-Gm; Thu, 01 Oct 2020 11:22:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kNwfG-0003Re-04 for linux-arm-kernel@lists.infradead.org; Thu, 01 Oct 2020 11:22:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 0709330E; Thu, 1 Oct 2020 04:22:16 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.51.119]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 2CC703F70D; Thu, 1 Oct 2020 04:22:14 -0700 (PDT) Date: Thu, 1 Oct 2020 12:22:05 +0100 From: Mark Rutland To: Will Deacon Subject: Re: [PATCH v2] arm64: dbm: Invalidate local TLB when setting TCR_EL1.HD Message-ID: <20201001112205.GA86680@C02TD0UTHF1T.local> References: <20201001110405.18617-1-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201001110405.18617-1-will@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201001_072222_130834_93748AAB X-CRM114-Status: GOOD ( 19.72 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Catalin Marinas , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 01, 2020 at 12:04:05PM +0100, Will Deacon wrote: > TCR_EL1.HD is permitted to be cached in a TLB, so invalidate the local > TLB after setting the bit when detected support for the feature. Although > this isn't strictly necessary, since we can happily operate with the bit > effectively clear, the current code uses an ISB in a half-hearted attempt > to make the change effective, so let's just fix that up. > > Cc: Catalin Marinas > Signed-off-by: Will Deacon Reviewed-by: Mark Rutland Mark. > --- > > v1 -> v2: Retain isb() prior to TLB invalidation. > > arch/arm64/kernel/cpufeature.c | 1 + > 1 file changed, 1 insertion(+) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6424584be01e..a474a4f39c95 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -1443,6 +1443,7 @@ static inline void __cpu_enable_hw_dbm(void) > > write_sysreg(tcr, tcr_el1); > isb(); > + local_flush_tlb_all(); > } > > static bool cpu_has_broken_dbm(void) > -- > 2.28.0.709.gb0816b6eb0-goog > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel