From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-13.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_GIT autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 56315C41604 for ; Tue, 6 Oct 2020 16:01:02 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EEC762075A for ; Tue, 6 Oct 2020 16:01:01 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="ecGzobRU" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EEC762075A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:MIME-Version:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:References:In-Reply-To:Message-Id:Date:Subject:To: From:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tlLCqX+FVmb3/E+qDJFaLnOk6KrzPftypTMydShW6xE=; b=ecGzobRUfNG+dtWptIQ6cRh9W4 ApObExYRUVkV2tSn31W8n/8mY0l8JQJQQ15DN/34TPu1jDmuaOg/N4a5tdlvVCvtRLvLYMB73a2+z 3PvK7S6qyqYYnioc5BRE/8P57fJxFDKQQxbGc/n7F6IfoIbnz6uEQNR7B6btnX8wxeCUnb1F+kY1c ptX2cwt9vDfHBZGsaXaAGTtsJ+WlOxdW3Uq/2GhxgkW2cQw0l1x/fabfzXNOvlpMP8sUGSj9SKT8L so95Z7vtvaUpM/mbCmMeUvOwEmAsDpw3hThvhsVv5GcxQEvGU/JZs3j6qgvu2g3hUX/49AYXtLlSx N3I0Gg0A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPpN6-0001nM-Ax; Tue, 06 Oct 2020 15:59:24 +0000 Received: from mga07.intel.com ([134.134.136.100]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kPpN0-0001lp-FW for linux-arm-kernel@lists.infradead.org; Tue, 06 Oct 2020 15:59:19 +0000 IronPort-SDR: pYeSE12Dn5zMtyPjewOtUlr8C1oJEhoe+8eUUryvczTppu4gAk7hhy8BnghVvXAnFKLAb11CO/ Dg4YFNEELpqQ== X-IronPort-AV: E=McAfee;i="6000,8403,9765"; a="228686874" X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="228686874" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga105.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Oct 2020 08:59:02 -0700 IronPort-SDR: 7Uy3gQritCHwk2RZmNr7mdsEdKYJJKpr6H1n+MrW0oMWsfgV/P9aVl7ehkbL8l44iq4w3be158 X5HAcpkvfe3w== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.77,343,1596524400"; d="scan'208";a="343826670" Received: from zulkifl3-ilbpg0.png.intel.com ([10.88.229.114]) by orsmga008.jf.intel.com with ESMTP; 06 Oct 2020 08:58:58 -0700 From: muhammad.husaini.zulkifli@intel.com To: adrian.hunter@intel.com, michal.simek@xilinx.com, sudeep.holla@arm.com, ulf.hansson@linaro.org, linux-mmc@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: [PATCH v3 1/2] mmc: sdhci-of-arasan: Enable UHS-1 support for Keem Bay SOC Date: Tue, 6 Oct 2020 23:55:48 +0800 Message-Id: <20201006155549.3595-2-muhammad.husaini.zulkifli@intel.com> X-Mailer: git-send-email 2.17.1 In-Reply-To: <20201006155549.3595-1-muhammad.husaini.zulkifli@intel.com> References: <20201006155549.3595-1-muhammad.husaini.zulkifli@intel.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201006_115918_668567_6D12147F X-CRM114-Status: GOOD ( 19.64 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: lakshmi.bai.raja.subramanian@intel.com, muhammad.husaini.zulkifli@intel.com, arnd@arndb.de, wan.ahmad.zainie.wan.mohamad@intel.com MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org From: Muhammad Husaini Zulkifli Voltage switching sequence is needed to support UHS-1 interface. There are 2 places to control the voltage. 1) By setting the AON register using firmware driver calling system-level platform management layer (SMC) to set the register. 2) By controlling the GPIO expander value to drive either 1.8V or 3.3V for power mux input. Signed-off-by: Muhammad Husaini Zulkifli Reviewed-by: Andy Shevchenko Reviewed-by: Adrian Hunter --- drivers/mmc/host/sdhci-of-arasan.c | 127 +++++++++++++++++++++++++++++ 1 file changed, 127 insertions(+) diff --git a/drivers/mmc/host/sdhci-of-arasan.c b/drivers/mmc/host/sdhci-of-arasan.c index f186fbd016b1..e681e6f860ba 100644 --- a/drivers/mmc/host/sdhci-of-arasan.c +++ b/drivers/mmc/host/sdhci-of-arasan.c @@ -16,6 +16,7 @@ */ #include +#include #include #include #include @@ -23,6 +24,7 @@ #include #include #include +#include #include "cqhci.h" #include "sdhci-pltfm.h" @@ -150,6 +152,7 @@ struct sdhci_arasan_data { struct regmap *soc_ctl_base; const struct sdhci_arasan_soc_ctl_map *soc_ctl_map; unsigned int quirks; + struct gpio_desc *uhs_gpio; /* Controller does not have CD wired and will not function normally without */ #define SDHCI_ARASAN_QUIRK_FORCE_CDTEST BIT(0) @@ -361,6 +364,113 @@ static int sdhci_arasan_voltage_switch(struct mmc_host *mmc, return -EINVAL; } +static int sdhci_arasan_keembay_voltage_switch(struct mmc_host *mmc, + struct mmc_ios *ios) +{ + struct sdhci_host *host = mmc_priv(mmc); + struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); + struct sdhci_arasan_data *sdhci_arasan = sdhci_pltfm_priv(pltfm_host); + u16 ctrl_2; + u16 clk; + int ret; + + switch (ios->signal_voltage) { + case MMC_SIGNAL_VOLTAGE_180: + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk &= ~SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + if (clk & SDHCI_CLOCK_CARD_EN) + return -EAGAIN; + + sdhci_writeb(host, SDHCI_POWER_ON | SDHCI_POWER_180, + SDHCI_POWER_CONTROL); + + /* + * Set VDDIO_B voltage to Low for 1.8V + * which is controlling by GPIO Expander. + */ + gpiod_set_value_cansleep(sdhci_arasan->uhs_gpio, 0); + + /* + * This is like final gatekeeper. Need to ensure changed voltage + * is settled before and after turn on this bit. + */ + usleep_range(1000, 1100); + + ret = keembay_sd_voltage_selection(KEEMBAY_SET_1V8_VOLT); + if (ret) + return ret; + + usleep_range(1000, 1100); + + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl_2 |= SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + /* Sleep for 5ms to stabilize 1.8V regulator */ + usleep_range(5000, 5500); + + /* 1.8V regulator output should be stable within 5 ms */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (!(ctrl_2 & SDHCI_CTRL_VDD_180)) + return -EAGAIN; + + clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL); + clk |= SDHCI_CLOCK_CARD_EN; + sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL); + break; + case MMC_SIGNAL_VOLTAGE_330: + /* + * Set VDDIO_B voltage to High for 3.3V + * which is controlling by GPIO Expander. + */ + gpiod_set_value_cansleep(sdhci_arasan->uhs_gpio, 1); + + /* + * This is like final gatekeeper. Need to ensure changed voltage + * is settled before and after turn on this bit. + */ + usleep_range(1000, 1100); + + ret = keembay_sd_voltage_selection(KEEMBAY_SET_3V3_VOLT); + if (ret) + return ret; + + usleep_range(1000, 1100); + + /* Set 1.8V Signal Enable in the Host Control2 register to 0 */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + ctrl_2 &= ~SDHCI_CTRL_VDD_180; + sdhci_writew(host, ctrl_2, SDHCI_HOST_CONTROL2); + + /* Sleep for 5ms to stabilize 3.3V regulator */ + usleep_range(5000, 5500); + + /* 3.3V regulator output should be stable within 5 ms */ + ctrl_2 = sdhci_readw(host, SDHCI_HOST_CONTROL2); + if (ctrl_2 & SDHCI_CTRL_VDD_180) + return -EAGAIN; + + break; + default: + return -EINVAL; + } + + return 0; +} + +static int sdhci_arasan_keembay_select_drive_strength(struct mmc_card *card, + unsigned int max_dtr, int host_drv, + int card_drv, int *drv_type) +{ + if (card->host->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_180) + *drv_type = MMC_SET_DRIVER_TYPE_C; + + return 0; +} + static const struct sdhci_ops sdhci_arasan_ops = { .set_clock = sdhci_arasan_set_clock, .get_max_clock = sdhci_pltfm_clk_get_max_clock, @@ -1521,6 +1631,7 @@ static int sdhci_arasan_probe(struct platform_device *pdev) struct sdhci_pltfm_host *pltfm_host; struct sdhci_arasan_data *sdhci_arasan; struct device_node *np = pdev->dev.of_node; + struct device *dev = &pdev->dev; const struct sdhci_arasan_of_data *data; match = of_match_node(sdhci_arasan_of_match, pdev->dev.of_node); @@ -1600,6 +1711,22 @@ static int sdhci_arasan_probe(struct platform_device *pdev) host->mmc->caps |= MMC_CAP_WAIT_WHILE_BUSY; } + if (of_device_is_compatible(np, "intel,keembay-sdhci-5.1-sd")) { + struct gpio_desc *uhs; + + uhs = devm_gpiod_get_optional(dev, "uhs", GPIOD_OUT_HIGH); + if (IS_ERR(uhs)) + return dev_err_probe(dev, PTR_ERR(uhs), "can't get uhs gpio\n"); + + sdhci_arasan->uhs_gpio = uhs; + + host->mmc_host_ops.start_signal_voltage_switch = + sdhci_arasan_keembay_voltage_switch; + + host->mmc_host_ops.select_drive_strength = + sdhci_arasan_keembay_select_drive_strength; + } + sdhci_arasan_update_baseclkfreq(host); ret = sdhci_arasan_register_sdclk(sdhci_arasan, clk_xin, &pdev->dev); -- 2.17.1 _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel