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[69.120.86.51]) by smtp.gmail.com with ESMTPSA id j9sm3907966qtk.89.2020.10.08.05.41.16 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 08 Oct 2020 05:41:17 -0700 (PDT) Date: Thu, 8 Oct 2020 08:41:13 -0400 From: Vivek Unune To: Andrew Lunn Subject: Re: [PATCH 1/3] ARM: dts: BCM5301X: Linksys EA9500 make use of pinctrl Message-ID: <20201008124113.GA5106@ubuntu> References: <6687de05226dd055ee362933d4841a12b038792d.1601655904.git.npcomplete13@gmail.com> <20201007210134.GD112961@lunn.ch> <20201007214633.GA1972@ubuntu> <20201008002621.GF112961@lunn.ch> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201008002621.GF112961@lunn.ch> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201008_084119_998620_078450F5 X-CRM114-Status: GOOD ( 25.23 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Hauke Mehrtens , =?utf-8?B?UmFmYcWCIE1pxYJlY2tp?= , linux-kernel@vger.kernel.org, Rob Herring , bcm-kernel-feedback-list@broadcom.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 08, 2020 at 02:26:21AM +0200, Andrew Lunn wrote: > On Wed, Oct 07, 2020 at 05:46:33PM -0400, Vivek Unune wrote: > > On Wed, Oct 07, 2020 at 11:01:34PM +0200, Andrew Lunn wrote: > > > On Wed, Oct 07, 2020 at 03:01:50PM -0400, Vivek Unune wrote: > > > > Forgo the use of mmioreg mdio mux infavor of the pinctrl > > > > > > Hi Vivek > > > > > > Could you add some more details please. I don't know this > > > hardware. I'm assuming there are two MDIO busses, external as talked > > > about in the comments, and an internal one? And for this hardware you > > > only need one of them? But i don't see what pinmux has to do with > > > this? > > Hi Andrew, > > > > There are indeed two mdio busses. To access the external bus, 9th bit > > of the mdio register has to be set. And to enable mii function, > > one has to set the registers 6 & 7 which is part of the pin controller. > > Earlier the pin controller was not defined and I resorted to use a > > combination of memory mapped io mux to change desired bits. > > > > Now that we have a pin controller - which is resposnsible for other > > functionality such as pwm, i2c, uart2, it makes sense to have a consistent > > device tree > > What makes it confusing is that you make multiple changes at once. It > would be easier to follow if you added the pinmux and removed the > mmioreg mux, and move the switch into the mdio-bus-mux node. Then in a > second patch rearrange the mdio-bus-mux. Small simple steps, with good > commit messages are much easier to follow and say, Yes, this is > correct. > Sure, le me declutter this. Thanks, Vivek _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel