From: Catalin Marinas <catalin.marinas@arm.com>
To: Qais Yousef <qais.yousef@arm.com>
Cc: linux-arch@vger.kernel.org, Will Deacon <will@kernel.org>,
"Peter Zijlstra \(Intel\)" <peterz@infradead.org>,
Marc Zyngier <maz@kernel.org>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Linus Torvalds <torvalds@linux-foundation.org>,
Morten Rasmussen <morten.rasmussen@arm.com>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [RFC PATCH 2/3] arm64: Add support for asymmetric AArch32 EL0 configurations
Date: Fri, 9 Oct 2020 10:39:58 +0100 [thread overview]
Message-ID: <20201009093957.GD23638@gaia> (raw)
In-Reply-To: <20201008181641.32767-3-qais.yousef@arm.com>
On Thu, Oct 08, 2020 at 07:16:40PM +0100, Qais Yousef wrote:
> diff --git a/arch/arm64/include/asm/cpu.h b/arch/arm64/include/asm/cpu.h
> index 7faae6ff3ab4..c920fa45e502 100644
> --- a/arch/arm64/include/asm/cpu.h
> +++ b/arch/arm64/include/asm/cpu.h
> @@ -15,6 +15,7 @@
> struct cpuinfo_arm64 {
> struct cpu cpu;
> struct kobject kobj;
> + bool aarch32_valid;
As I replied to Greg, I think we can drop this field entirely. But, of
course, please check that the kernel doesn't get tainted if booting on a
non-32-bit capable CPU.
> void cpuinfo_store_cpu(void)
> {
> struct cpuinfo_arm64 *info = this_cpu_ptr(&cpu_data);
> __cpuinfo_store_cpu(info);
> + if (id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0))
> + __cpuinfo_store_cpu_32bit(info);
> + /*
> + * With asymmetric AArch32 support, populate the boot CPU information
> + * on the first 32-bit capable secondary CPU if the primary one
> + * skipped this step.
> + */
> + if (IS_ENABLED(CONFIG_ASYMMETRIC_AARCH32) &&
> + !boot_cpu_data.aarch32_valid &&
> + id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0)) {
> + __cpuinfo_store_cpu_32bit(&boot_cpu_data);
> + init_cpu_32bit_features(&boot_cpu_data);
> + }
Same here, we can probably drop the boot_cpu_data update here.
> diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c
> index 077293b5115f..0b9aaee1df59 100644
> --- a/arch/arm64/kvm/sys_regs.c
> +++ b/arch/arm64/kvm/sys_regs.c
> @@ -1131,6 +1131,16 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu,
> if (!vcpu_has_sve(vcpu))
> val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT);
> val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT);
> +
> + if (!system_supports_sym_32bit_el0()) {
> + /*
> + * We could be running on asym aarch32 system.
> + * Override to present a aarch64 only system.
> + */
> + val &= ~(0xfUL << ID_AA64PFR0_EL0_SHIFT);
> + val |= (ID_AA64PFR0_EL0_64BIT_ONLY << ID_AA64PFR0_EL0_SHIFT);
> + }
With the sanitised registers using the lowest value of this field, I
think we no longer need this explicit masking.
--
Catalin
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next prev parent reply other threads:[~2020-10-09 9:41 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-08 18:16 [RFC PATCH 0/3] Add support for Asymmetric AArch32 systems Qais Yousef
2020-10-08 18:16 ` [RFC PATCH 1/3] arm64: kvm: Handle " Qais Yousef
2020-10-09 8:12 ` Marc Zyngier
2020-10-09 9:58 ` Qais Yousef
2020-10-09 12:34 ` Marc Zyngier
2020-10-09 12:48 ` Qais Yousef
2020-10-12 15:32 ` James Morse
2020-10-13 10:32 ` Marc Zyngier
2020-10-13 11:51 ` James Morse
2020-10-13 11:59 ` Qais Yousef
2020-10-13 12:09 ` Marc Zyngier
2020-10-13 12:16 ` Qais Yousef
2020-10-08 18:16 ` [RFC PATCH 2/3] arm64: Add support for asymmetric AArch32 EL0 configurations Qais Yousef
2020-10-08 18:22 ` Randy Dunlap
2020-10-12 10:22 ` Qais Yousef
2020-10-09 6:13 ` Greg Kroah-Hartman
2020-10-09 8:40 ` Will Deacon
2020-10-09 8:50 ` Catalin Marinas
2020-10-09 9:39 ` Catalin Marinas [this message]
2020-10-12 12:46 ` Qais Yousef
2020-10-08 18:16 ` [RFC PATCH 3/3] arm64: Handle AArch32 tasks running on non AArch32 cpu Qais Yousef
2020-10-09 7:29 ` Peter Zijlstra
2020-10-09 8:13 ` Morten Rasmussen
2020-10-09 8:31 ` Will Deacon
2020-10-09 8:50 ` Morten Rasmussen
2020-10-09 9:33 ` Catalin Marinas
2020-10-09 9:42 ` Greg Kroah-Hartman
2020-10-09 11:31 ` Qais Yousef
2020-10-09 12:40 ` Catalin Marinas
2020-10-13 14:23 ` Qais Yousef
2020-10-09 9:25 ` Peter Zijlstra
2020-10-09 9:39 ` Qais Yousef
2020-10-09 9:51 ` Catalin Marinas
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