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[209.6.122.159]) by smtp.gmail.com with ESMTPSA id p3sm8397082qkj.113.2020.10.10.08.13.08 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Sat, 10 Oct 2020 08:13:09 -0700 (PDT) Date: Sat, 10 Oct 2020 11:13:07 -0400 From: Masayoshi Mizuma To: Marc Zyngier Subject: Re: [PATCH v4 1/5] arm64: Add framework to turn IPI as NMI Message-ID: <20201010151307.vq74if4mndjn4nhm@gabell> References: <1599830924-13990-1-git-send-email-sumit.garg@linaro.org> <1599830924-13990-2-git-send-email-sumit.garg@linaro.org> <20201010015855.vksetnj4luft5enc@gabell> <877drypgqb.wl-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <877drypgqb.wl-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201010_111313_627574_5EEFD6DF X-CRM114-Status: GOOD ( 17.67 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, Sumit Garg , daniel.thompson@linaro.org, jason@lakedaemon.net, catalin.marinas@arm.com, jason.wessel@windriver.com, dianders@chromium.org, linux-kernel@vger.kernel.org, julien.thierry.kdev@gmail.com, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, will@kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Sat, Oct 10, 2020 at 10:34:04AM +0100, Marc Zyngier wrote: > On Sat, 10 Oct 2020 02:58:55 +0100, > Masayoshi Mizuma wrote: > > [...] > > > > +void ipi_nmi_setup(int cpu) > > > +{ > > > + if (!ipi_desc) > > > + return; > > > > ipi_nmi_setup() may be called twice for CPU0: > > > > set_smp_ipi_range => set_smp_ipi_nmi => ipi_nmi_setup > > => ipi_setup => ipi_nmi_setup > > > > Actually, I got the following error message via the second ipi_nmi_setup(): > > > > GICv3: Pseudo-NMIs enabled using relaxed ICC_PMR_EL1 synchronisation > > GICv3: Cannot set NMI property of enabled IRQ 8 > > genirq: Failed to setup NMI delivery: irq 8 > > > > Why don't we have a check to prevent that? Like as: > > > > if (cpumask_test_cpu(cpu, ipi_desc->percpu_enabled)) > > return; > > That's definitely the wrong thing to do. prepare_nmi_setup() shouldn't > be called twice, and papering over it isn't acceptable. Got it. How about moving ipi_nmi_setup() from ipi_setup() to secondary_start_kernel() ? so that CPU0 can call ipi_nmi_setup() only from set_smp_ipi_nmi(). --- a/arch/arm64/kernel/smp.c +++ b/arch/arm64/kernel/smp.c @@ -245,6 +245,7 @@ asmlinkage notrace void secondary_start_kernel(void) notify_cpu_starting(cpu); ipi_setup(cpu); + ipi_nmi_setup(cpu); store_cpu_topology(cpu); numa_add_cpu(cpu); @@ -966,8 +967,6 @@ static void ipi_setup(int cpu) for (i = 0; i < nr_ipi; i++) enable_percpu_irq(ipi_irq_base + i, 0); - - ipi_nmi_setup(cpu); } #ifdef CONFIG_HOTPLUG_CPU Thanks, Masa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel