From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 57359C433E7 for ; Mon, 19 Oct 2020 12:26:47 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id CB75822268 for ; Mon, 19 Oct 2020 12:26:46 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="X8lRnRvz" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org CB75822268 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=V8lmyWEaM/NUORnjnuWSjKWpaW8i4J2L7U3hzNUQyX0=; b=X8lRnRvzv+dhMTRm+NBxma065 G632L9Zb02x4gbA44au0GEden8fDuMOo/qE2dLvt30lYO9U1i6FJRJuX9/MNAF5/FSEGK4gW6o0KM wplcKheeEjiJrX4Mo7a1NHDkYd9dOWyDmBTkl3edrSaBD9g0aV+90u/d05b47FfvZqJVWPjqVipjx 8YIiUvJo3NsQsBbf9jeb3IOL6TYxOJqLrkw/DHuRmchlxAEsNlFZ35WWacVbGRLTpIwR7uWKzD2LI rOVxGQKRzfAOMy5F1V8w6euSdjId7B/EGGeTDP0trfkE8UZABJRFCbTNVnOckznoeI3W2bBbDiTkE 00Ii8qYpA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kUUDq-00026C-SO; Mon, 19 Oct 2020 12:25:06 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kUUDo-00025N-Iq for linux-arm-kernel@lists.infradead.org; Mon, 19 Oct 2020 12:25:05 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 64B3730E; Mon, 19 Oct 2020 05:25:00 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.55.56]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 35F743F719; Mon, 19 Oct 2020 05:24:58 -0700 (PDT) Date: Mon, 19 Oct 2020 13:24:55 +0100 From: Mark Rutland To: Alexandru Elisei Subject: Re: [PATCH] perf: arm_spe: Use Inner Shareable DSB when draining the buffer Message-ID: <20201019122455.GD34028@C02TD0UTHF1T.local> References: <20201006150520.161985-1-alexandru.elisei@arm.com> <87ft6r4bgd.wl-maz@kernel.org> <8fa8af94-ab08-b43a-95e4-55a13de09efe@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <8fa8af94-ab08-b43a-95e4-55a13de09efe@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201019_082504_714770_4F4EF94A X-CRM114-Status: GOOD ( 28.65 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: suzuki.poulose@arm.com, Marc Zyngier , linux-kernel@vger.kernel.org, james.morse@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, kvmarm@lists.cs.columbia.edu, julien.thierry.kdev@gmail.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 06, 2020 at 05:13:31PM +0100, Alexandru Elisei wrote: > Hi Marc, > > Thank you for having a look at the patch! > > On 10/6/20 4:32 PM, Marc Zyngier wrote: > > Hi Alex, > > > > On Tue, 06 Oct 2020 16:05:20 +0100, > > Alexandru Elisei wrote: > >> From ARM DDI 0487F.b, page D9-2807: > >> > >> "Although the Statistical Profiling Extension acts as another observer in > >> the system, for determining the Shareability domain of the DSB > >> instructions, the writes of sample records are treated as coming from the > >> PE that is being profiled." > >> > >> Similarly, on page D9-2801: > >> > >> "The memory type and attributes that are used for a write by the > >> Statistical Profiling Extension to the Profiling Buffer is taken from the > >> translation table entries for the virtual address being written to. That > >> is: > >> - The writes are treated as coming from an observer that is coherent with > >> all observers in the Shareability domain that is defined by the > >> translation tables." > >> > >> All the PEs are in the Inner Shareable domain, use a DSB ISH to make sure > >> writes to the profiling buffer have completed. > > I'm a bit sceptical of this change. The SPE writes are per-CPU, and > > all we are trying to ensure is that the CPU we are running on has > > drained its own queue of accesses. > > > > The accesses being made within the IS domain doesn't invalidate the > > fact that they are still per-CPU, because "the writes of sample > > records are treated as coming from the PE that is being profiled.". > > > > So why should we have an IS-wide synchronisation for accesses that are > > purely local? > > I think I might have misunderstood how perf spe works. Below is my original train > of thought. > > In the buffer management event interrupt we drain the buffer, and if the buffer is > full, we call arm_spe_perf_aux_output_end() -> perf_aux_output_end(). The comment > for perf_aux_output_end() says "Commit the data written by hardware into the ring > buffer by adjusting aux_head and posting a PERF_RECORD_AUX into the perf buffer. > It is the pmu driver's responsibility to observe ordering rules of the hardware, > so that all the data is externally visible before this is called." My conclusion > was that after we drain the buffer, the data must be visible to all CPUs. FWIW, this reasoning sounds correct to me. The DSB NSH will be sufficient to drain the buffer, but we need the DSB ISH to ensure that it's visbile to other CPUs at the instant we call perf_aux_output_end(). Otherwise, if CPU x is reading the ring-buffer written by CPU y, it might see the aux buffer pointers updated before the samples are viisble, and hence read junk from the buffer. We can add a comment to that effect (or rework perf_aux_output_end() somehow to handle that ordering). Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel