From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 5D6C6C388F9 for ; Wed, 21 Oct 2020 13:23:49 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E541C221FC for ; Wed, 21 Oct 2020 13:23:48 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="FP5QWVz6" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E541C221FC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=hg8WJKy4uxBQE4iw4Zapu061eVihdCFwUzNVHJRoz1A=; b=FP5QWVz6WkhvAS0CUUiPrECTe Hn7tZeRNeApOvzrtCF5fACLcipzfcEUu5kS00W0ilNZBa6bLbipAy8Zr5PJVeqiakBkXOOE45XwRg YAeY96ISX/SeHyV4LaTnfUyBXg89sDcTUQdZBOHq1SwAFYp5lsh7MPPQqUFhetJu5TIYB6OLvqUC2 gihoRtwh1tdplNH/SjlN/0GS0Udfx9tAPAz9Rd7Iq6gO5vmx7dknd37eDNSn23jXjP94RvInvpp45 F/jhLeH9L1y3jiDeYdmXoUWBKD6uDNYyo4k3U1JljkrNpo/WsNrh2q/sWUvmWGv8n7aICV9/HiUl8 iVwlWH0KQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVE4I-0005FT-8u; Wed, 21 Oct 2020 13:22:18 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVE4C-0005Ce-HN for linux-arm-kernel@lists.infradead.org; Wed, 21 Oct 2020 13:22:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 03E5E31B; Wed, 21 Oct 2020 06:22:12 -0700 (PDT) Received: from e107158-lin (e107158-lin.cambridge.arm.com [10.1.194.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id A98583F66B; Wed, 21 Oct 2020 06:22:10 -0700 (PDT) Date: Wed, 21 Oct 2020 14:22:08 +0100 From: Qais Yousef To: Greg Kroah-Hartman Subject: Re: [RFC PATCH v2 4/4] arm64: Export id_aar64fpr0 via sysfs Message-ID: <20201021132208.6lb55o7worihkznv@e107158-lin> References: <20201021104611.2744565-1-qais.yousef@arm.com> <20201021104611.2744565-5-qais.yousef@arm.com> <20201021112818.GC1141598@kroah.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201021112818.GC1141598@kroah.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201021_092212_712233_AEC287CC X-CRM114-Status: GOOD ( 28.11 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Will Deacon , "Peter Zijlstra \(Intel\)" , Catalin Marinas , James Morse , Marc Zyngier , Linus Torvalds , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/21/20 13:28, Greg Kroah-Hartman wrote: > On Wed, Oct 21, 2020 at 11:46:11AM +0100, Qais Yousef wrote: > > So that userspace can detect if the cpu has aarch32 support at EL0. > > > > CPUREGS_ATTR_RO() was renamed to CPUREGS_RAW_ATTR_RO() to better reflect > > what it does. And fixed to accept both u64 and u32 without causing the > > printf to print out a warning about mismatched type. This was caught > > while testing to check the new CPUREGS_USER_ATTR_RO(). > > > > The new CPUREGS_USER_ATTR_RO() exports a Sanitised or RAW sys_reg based > > on a @cond to user space. The exported fields match the definition in > > arm64_ftr_reg so that the content of a register exported via MRS and > > sysfs are kept cohesive. > > > > The @cond in our case is that the system is asymmetric aarch32 and the > > controlling sysctl.enable_asym_32bit is enabled. > > > > Update Documentation/arm64/cpu-feature-registers.rst to reflect the > > newly visible EL0 field in ID_AA64FPR0_EL1. > > > > Note that the MRS interface will still return the sanitized content > > _only_. > > > > Signed-off-by: Qais Yousef > > --- > > > > Example output. I was surprised that the 2nd field (bits[7:4]) is printed out > > although it's set as FTR_HIDDEN. > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000011 > > > > # echo 1 > /proc/sys/kernel/enable_asym_32bit > > > > # cat /sys/devices/system/cpu/cpu*/regs/identification/id_aa64pfr0 > > 0x0000000000000011 > > 0x0000000000000011 > > 0x0000000000000012 > > 0x0000000000000012 > > 0x0000000000000011 > > 0x0000000000000011 > > > > Documentation/arm64/cpu-feature-registers.rst | 2 +- > > arch/arm64/kernel/cpufeature.c | 2 +- > > arch/arm64/kernel/cpuinfo.c | 58 +++++++++++++++++-- > > 3 files changed, 54 insertions(+), 8 deletions(-) > > > > diff --git a/Documentation/arm64/cpu-feature-registers.rst b/Documentation/arm64/cpu-feature-registers.rst > > index f28853f80089..bfcbda6d6f35 100644 > > --- a/Documentation/arm64/cpu-feature-registers.rst > > +++ b/Documentation/arm64/cpu-feature-registers.rst > > @@ -166,7 +166,7 @@ infrastructure: > > +------------------------------+---------+---------+ > > | EL1 | [7-4] | n | > > +------------------------------+---------+---------+ > > - | EL0 | [3-0] | n | > > + | EL0 | [3-0] | y | > > +------------------------------+---------+---------+ > > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > index 6f795c8221f4..0f7307c8ad80 100644 > > --- a/arch/arm64/kernel/cpufeature.c > > +++ b/arch/arm64/kernel/cpufeature.c > > @@ -221,7 +221,7 @@ static const struct arm64_ftr_bits ftr_id_aa64pfr0[] = { > > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL3_SHIFT, 4, 0), > > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL2_SHIFT, 4, 0), > > ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL1_SHIFT, 4, ID_AA64PFR0_EL1_64BIT_ONLY), > > - ARM64_FTR_BITS(FTR_HIDDEN, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), > > + ARM64_FTR_BITS(FTR_VISIBLE, FTR_NONSTRICT, FTR_LOWER_SAFE, ID_AA64PFR0_EL0_SHIFT, 4, ID_AA64PFR0_EL0_64BIT_ONLY), > > ARM64_FTR_END, > > }; > > > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > > index 93c55986ca7f..632b9d5b5230 100644 > > --- a/arch/arm64/kernel/cpuinfo.c > > +++ b/arch/arm64/kernel/cpuinfo.c > > @@ -231,25 +231,71 @@ static struct kobj_type cpuregs_kobj_type = { > > * future expansion without an ABI break. > > */ > > #define kobj_to_cpuinfo(kobj) container_of(kobj, struct cpuinfo_arm64, kobj) > > -#define CPUREGS_ATTR_RO(_name, _field) \ > > +#define CPUREGS_RAW_ATTR_RO(_name, _field) \ > > static ssize_t _name##_show(struct kobject *kobj, \ > > struct kobj_attribute *attr, char *buf) \ > > { \ > > struct cpuinfo_arm64 *info = kobj_to_cpuinfo(kobj); \ > > \ > > - if (info->reg_midr) \ > > - return sprintf(buf, "0x%016x\n", info->reg_##_field); \ > > - else \ > > + if (info->reg_midr) { \ > > + u64 val = info->reg_##_field; \ > > + return sprintf(buf, "0x%016llx\n", val); \ > > Nit, for sysfs, use the new sysfs_emit() call instead of sprintf(). Will do. Thanks! -- Qais Yousef _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel