From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 68C63C388F9 for ; Wed, 21 Oct 2020 16:22:46 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0100A21481 for ; Wed, 21 Oct 2020 16:22:45 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="zxpJHiKT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0100A21481 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tP6eUSaujoScIungcISb5qeFJHJzDq8Jzd5O0udRNqQ=; b=zxpJHiKT65ayd80Be0h/sijx8 P1qQ3CPBNQgRpa/nO86e1feXkupZXDC0U3jUoLk/m5fgWkmPEMPgCEQYYLhclW10iRf2nuOGYgvzt 7kO+NX0tFAr/09pIB459LAjwyhQm0N2G68KjFKujU8i5OwMHxW6av4GlthXvvNi8K4ZRgzWP73i9U buqrryZsaK4gIQBhdD1le/f9ubLsbps9/5W5pEkyMexMaDYSzq2ljNH8K8At6T9WNiGV19OgqK6OD nGmw8z5weM/ybGsZe8kqHBD+uoY58A8UO0W4ln/8dBza/IMuJGjJhk/866ZcynGEkz2PXS9su6VDh jMPKhYPHg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVGrh-0003hY-O7; Wed, 21 Oct 2020 16:21:29 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kVGrf-0003gf-1q for linux-arm-kernel@lists.infradead.org; Wed, 21 Oct 2020 16:21:28 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id CF5B2D6E; Wed, 21 Oct 2020 09:21:25 -0700 (PDT) Received: from e107158-lin (e107158-lin.cambridge.arm.com [10.1.194.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 725CD3F719; Wed, 21 Oct 2020 09:21:24 -0700 (PDT) Date: Wed, 21 Oct 2020 17:21:21 +0100 From: Qais Yousef To: Will Deacon Subject: Re: [RFC PATCH v2 2/4] arm64: Add support for asymmetric AArch32 EL0 configurations Message-ID: <20201021162121.bdiopxvzscbhzzpt@e107158-lin> References: <20201021104611.2744565-1-qais.yousef@arm.com> <20201021104611.2744565-3-qais.yousef@arm.com> <20201021153911.GC18071@willie-the-truck> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201021153911.GC18071@willie-the-truck> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201021_122127_248436_BAFBF0E1 X-CRM114-Status: GOOD ( 29.76 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , "Peter Zijlstra \(Intel\)" , Catalin Marinas , James Morse , Greg Kroah-Hartman , Linus Torvalds , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On 10/21/20 16:39, Will Deacon wrote: > On Wed, Oct 21, 2020 at 11:46:09AM +0100, Qais Yousef wrote: > > When the CONFIG_ASYMMETRIC_AARCH32 option is enabled (EXPERT), the type > > of the ARM64_HAS_32BIT_EL0 capability becomes WEAK_LOCAL_CPU_FEATURE. > > The kernel will now return true for system_supports_32bit_el0() and > > checks 32-bit tasks are affined to AArch32 capable CPUs only in > > do_notify_resume(). If the affinity contains a non-capable AArch32 CPU, > > the tasks will get SIGKILLed. If the last CPU supporting 32-bit is > > offlined, the kernel will SIGKILL any scheduled 32-bit tasks (the > > alternative is to prevent offlining through a new .cpu_disable feature > > entry). > > > > In addition to the relaxation of the ARM64_HAS_32BIT_EL0 capability, > > this patch factors out the 32-bit cpuinfo and features setting into > > separate functions: __cpuinfo_store_cpu_32bit(), > > init_cpu_32bit_features(). The cpuinfo of the booting CPU > > (boot_cpu_data) is now updated on the first 32-bit capable CPU even if > > it is a secondary one. The ID_AA64PFR0_EL0_64BIT_ONLY feature is relaxed > > to FTR_NONSTRICT and FTR_HIGHER_SAFE when the asymmetric AArch32 support > > is enabled. The compat_elf_hwcaps are only verified for the > > AArch32-capable CPUs to still allow hotplugging AArch64-only CPUs. > > > > Make sure that KVM never sees the asymmetric 32bit system. Guest can > > still ignore ID registers and force run 32bit at EL0. > > > > Co-developed-by: Qais Yousef > > Signed-off-by: Catalin Marinas > > Signed-off-by: Qais Yousef > > [...] > > > diff --git a/arch/arm64/include/asm/thread_info.h b/arch/arm64/include/asm/thread_info.h > > index 5e784e16ee89..312974ab2c85 100644 > > --- a/arch/arm64/include/asm/thread_info.h > > +++ b/arch/arm64/include/asm/thread_info.h > > @@ -67,6 +67,7 @@ void arch_release_task_struct(struct task_struct *tsk); > > #define TIF_FOREIGN_FPSTATE 3 /* CPU's FP state is not current's */ > > #define TIF_UPROBE 4 /* uprobe breakpoint or singlestep */ > > #define TIF_FSCHECK 5 /* Check FS is USER_DS on return */ > > +#define TIF_CHECK_32BIT_AFFINITY 6 /* Check thread affinity for asymmetric AArch32 */ > > I've looked through the patch and I still can't figure out why this extra > flag is needed. We know if a CPU supports 32-bit EL0, and we know whether > or not a task is 32-bit. So why the extra flag? Is it just a hangover from > the old series? It did evolve a bit organically. AFAICS it helps as an optimization to avoid the checks unnecessarily. If it's not expensive to do the checks in the loop in do_notify_resume() we can omit it. We will still protect it with system_supports_asym_32bit_el0() so the check is done on these systems only. Thanks -- Qais Yousef _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel