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Fri, 23 Oct 2020 02:52:31 -0700 (PDT) Received: from kozik-lap ([194.230.155.171]) by smtp.googlemail.com with ESMTPSA id p4sm506224eji.105.2020.10.23.02.52.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 23 Oct 2020 02:52:30 -0700 (PDT) Date: Fri, 23 Oct 2020 11:52:27 +0200 From: Krzysztof Kozlowski To: Adam Ford Subject: Re: [PATCH 3/4] arm64: dts: imx8mn: add GPC node and power domains Message-ID: <20201023095227.GE42872@kozik-lap> References: <20201022150808.763082-1-aford173@gmail.com> <20201022150808.763082-4-aford173@gmail.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201022150808.763082-4-aford173@gmail.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201023_055233_315355_5EF71C7A X-CRM114-Status: GOOD ( 18.24 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: marex@denx.de, devicetree@vger.kernel.org, Andrey Smirnov , Fabio Estevam , Sascha Hauer , aford@beaconembedded.com, linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Shawn Guo , linux-arm-kernel@lists.infradead.org, l.stach@pengutronix.de Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Oct 22, 2020 at 10:08:06AM -0500, Adam Ford wrote: > This adds the DT nodes to describe the power domains available on the > i.MX8MN. There are four power domains, but the displaymix and mipi > power domains need a separate clock block controller which is also > pending for 8MP and 8MM. Once the path for those is clear, Nano will > need something similar, but the registers for Nano differ. For now, > the dispmix and mipi are placeholders. > > Signed-off-by: Adam Ford > > diff --git a/arch/arm64/boot/dts/freescale/imx8mn.dtsi b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > index 9b4baf7bdfb1..27733fbe87e9 100644 > --- a/arch/arm64/boot/dts/freescale/imx8mn.dtsi > +++ b/arch/arm64/boot/dts/freescale/imx8mn.dtsi > @@ -596,6 +596,55 @@ src: reset-controller@30390000 { > interrupts = ; > #reset-cells = <1>; > }; > + > + gpc: gpc@303a0000 { > + compatible = "fsl,imx8mn-gpc"; > + reg = <0x303a0000 0x10000>; > + interrupt-parent = <&gic>; > + interrupt-controller; > + #interrupt-cells = <3>; Missing interrupts. > + > + pgc { > + #address-cells = <1>; > + #size-cells = <0>; > + > + pgc_hsiomix: power-domain@0 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MN_CLK_USB_BUS>; > + }; > + > + pgc_otg1: power-domain@1 { > + #power-domain-cells = <0>; > + reg = ; > + power-domains = <&pgc_hsiomix>; > + }; > + > + pgc_gpumix: power-domain@2 { > + #power-domain-cells = <0>; > + reg = ; > + clocks = <&clk IMX8MN_CLK_GPU_CORE_ROOT>, > + <&clk IMX8MN_CLK_GPU_SHADER_DIV>, > + <&clk IMX8MN_CLK_GPU_BUS_ROOT>, > + <&clk IMX8MN_CLK_GPU_AHB>; > + resets = <&src IMX8MQ_RESET_GPU_RESET>; Does it compile without include? Did the include come via dependencies of this patch? Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel