From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A30E2C4363A for ; Mon, 26 Oct 2020 14:07:36 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 566C222250 for ; Mon, 26 Oct 2020 14:07:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="c7sQFu1U" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 566C222250 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=ublzTkKJT9dkLQXur8hOtFrqFvC/nXdauEAkMs3JN4E=; b=c7sQFu1UyRzv7uqk8IwqAtR+6 RKRw9LvX41bArjZXzmvmCix+XM5skFL2Wt/lWuwm8qyBd835FbQUSsdjlMzdQzr7rdogcy2JRgSgu nNkfSw873vlIJm+wEmps1U5JFtEUm4IOJHhRDN1cZ0d85yobrTKaJLG1pDE31zyHWk3/cLC8t4V+4 Z/DqH6T9T/FITUW0xIwwJ3KjDnb4lScEZ0+Vs/1FgHnSIvlzxtEZ6/vQxVQ35jI7mzqwF7eJQpP0m R/jpjjP022W8scCA1avzo1MzsiB6ks2pL+rssT7KCoh5WD7hw6GOwjibWATSez3bsPFCrkmJMaVm2 gnymGvLUQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX38a-000434-B4; Mon, 26 Oct 2020 14:06:16 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX38X-00042B-5P for linux-arm-kernel@lists.infradead.org; Mon, 26 Oct 2020 14:06:14 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id DAA5030E; Mon, 26 Oct 2020 07:06:10 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.56.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 3CE573F68F; Mon, 26 Oct 2020 07:06:09 -0700 (PDT) Date: Mon, 26 Oct 2020 14:06:06 +0000 From: Mark Rutland To: Marc Zyngier Subject: Re: [PATCH 04/11] KVM: arm64: Move PC rollback on SError to HYP Message-ID: <20201026140606.GF12454@C02TD0UTHF1T.local> References: <20201026133450.73304-1-maz@kernel.org> <20201026133450.73304-5-maz@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201026133450.73304-5-maz@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_100613_321069_A9CA6D20 X-CRM114-Status: GOOD ( 25.62 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Will Deacon , kernel-team@android.com, kvmarm@lists.cs.columbia.edu, linux-arm-kernel@lists.infradead.org, kvm@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 26, 2020 at 01:34:43PM +0000, Marc Zyngier wrote: > Instead of handling the "PC rollback on SError during HVC" at EL1 (which > requires disclosing PC to a potentially untrusted kernel), let's move > this fixup to ... fixup_guest_exit(), which is where we do all fixups. > > Isn't that neat? > > Signed-off-by: Marc Zyngier Acked-by: Mark Rutland Mark. > --- > arch/arm64/kvm/handle_exit.c | 17 ----------------- > arch/arm64/kvm/hyp/include/hyp/switch.h | 15 +++++++++++++++ > 2 files changed, 15 insertions(+), 17 deletions(-) > > diff --git a/arch/arm64/kvm/handle_exit.c b/arch/arm64/kvm/handle_exit.c > index d4e00a864ee6..f79137ee4274 100644 > --- a/arch/arm64/kvm/handle_exit.c > +++ b/arch/arm64/kvm/handle_exit.c > @@ -241,23 +241,6 @@ int handle_exit(struct kvm_vcpu *vcpu, int exception_index) > { > struct kvm_run *run = vcpu->run; > > - if (ARM_SERROR_PENDING(exception_index)) { > - u8 esr_ec = ESR_ELx_EC(kvm_vcpu_get_esr(vcpu)); > - > - /* > - * HVC already have an adjusted PC, which we need to > - * correct in order to return to after having injected > - * the SError. > - * > - * SMC, on the other hand, is *trapped*, meaning its > - * preferred return address is the SMC itself. > - */ > - if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) > - *vcpu_pc(vcpu) -= 4; > - > - return 1; > - } > - > exception_index = ARM_EXCEPTION_CODE(exception_index); > > switch (exception_index) { > diff --git a/arch/arm64/kvm/hyp/include/hyp/switch.h b/arch/arm64/kvm/hyp/include/hyp/switch.h > index d687e574cde5..668f02c7b0b3 100644 > --- a/arch/arm64/kvm/hyp/include/hyp/switch.h > +++ b/arch/arm64/kvm/hyp/include/hyp/switch.h > @@ -411,6 +411,21 @@ static inline bool fixup_guest_exit(struct kvm_vcpu *vcpu, u64 *exit_code) > if (ARM_EXCEPTION_CODE(*exit_code) != ARM_EXCEPTION_IRQ) > vcpu->arch.fault.esr_el2 = read_sysreg_el2(SYS_ESR); > > + if (ARM_SERROR_PENDING(*exit_code)) { > + u8 esr_ec = kvm_vcpu_trap_get_class(vcpu); > + > + /* > + * HVC already have an adjusted PC, which we need to > + * correct in order to return to after having injected > + * the SError. > + * > + * SMC, on the other hand, is *trapped*, meaning its > + * preferred return address is the SMC itself. > + */ > + if (esr_ec == ESR_ELx_EC_HVC32 || esr_ec == ESR_ELx_EC_HVC64) > + *vcpu_pc(vcpu) -= 4; > + } > + > /* > * We're using the raw exception code in order to only process > * the trap if no SError is pending. We will come back to the > -- > 2.28.0 > > _______________________________________________ > kvmarm mailing list > kvmarm@lists.cs.columbia.edu > https://lists.cs.columbia.edu/mailman/listinfo/kvmarm _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel