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Mon, 26 Oct 2020 12:55:38 -0400 (EDT) Date: Mon, 26 Oct 2020 17:55:36 +0100 From: Maxime Ripard To: Paul Kocialkowski Subject: Re: [PATCH 10/14] ARM: dts: sun8i: v3s: Add MIPI D-PHY and MIPI CSI-2 interface nodes Message-ID: <20201026165536.glmo727mzixtrtq5@gilmour.lan> References: <20201023174546.504028-1-paul.kocialkowski@bootlin.com> <20201023174546.504028-11-paul.kocialkowski@bootlin.com> MIME-Version: 1.0 In-Reply-To: <20201023174546.504028-11-paul.kocialkowski@bootlin.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_125539_619238_99174F4E X-CRM114-Status: GOOD ( 15.28 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devel@driverdev.osuosl.org, devicetree@vger.kernel.org, Philipp Zabel , Kishon Vijay Abraham I , Thomas Petazzoni , Greg Kroah-Hartman , Helen Koike , linux-kernel@vger.kernel.org, Chen-Yu Tsai , Hans Verkuil , linux-sunxi@googlegroups.com, Rob Herring , Vinod Koul , Yong Deng , Sakari Ailus , Hans Verkuil , Mauro Carvalho Chehab , kevin.lhopital@hotmail.com, linux-arm-kernel@lists.infradead.org, linux-media@vger.kernel.org Content-Type: multipart/mixed; boundary="===============0839880583116115496==" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org --===============0839880583116115496== Content-Type: multipart/signed; micalg=pgp-sha256; protocol="application/pgp-signature"; boundary="zcfibetqyhgzzpse" Content-Disposition: inline --zcfibetqyhgzzpse Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable On Fri, Oct 23, 2020 at 07:45:42PM +0200, Paul Kocialkowski wrote: > MIPI CSI-2 is supported on the V3s with an A31 controller, which seems > to be used on all Allwinner chips supporting it, except for the A83T. > The controller is connected to CSI0 through fwnode endpoints. > The mipi_csi2_in port node is provided to connect MIPI CSI-2 sensors. >=20 > The D-PHY part is the same that already drives DSI, but used in Rx mode. >=20 > Signed-off-by: Paul Kocialkowski Especially since you haven't tested CSI0 without MIPI-CSI, you can squash that patch into the previous one. Maxime --zcfibetqyhgzzpse Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iHUEABYIAB0WIQRcEzekXsqa64kGDp7j7w1vZxhRxQUCX5b/iAAKCRDj7w1vZxhR xbAjAP9CP/SEWp6kG8clryOH7rRuMR0ZbxY3MUewfpakLBpAAgEAukaJS8Bwt8EA oXawwEY8ttfUtVYweh72ULszOhy2SAk= =152k -----END PGP SIGNATURE----- --zcfibetqyhgzzpse-- --===============0839880583116115496== Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit Content-Disposition: inline _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel --===============0839880583116115496==--