From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 492BBC4363A for ; Mon, 26 Oct 2020 17:03:22 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0606520756 for ; Mon, 26 Oct 2020 17:03:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="k8vCel3/" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0606520756 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=R05qb7yrcpgZ2QhoDYcaw2fsDkdo3s0SQVaHQqdsc+4=; b=k8vCel3/MXr+De21/7pNF6BXz 2yMLK6d9HtmoMTayf+dCBRY+5KIaBbDC/P/hmjMHOwOhdbcnkqbMTAYO6tXpa0VDCeshMrc4ndd/a MQVN4fftJafqwGNr7XvD9sSYtRXOaXoYQfV/DbA101IaQ9t8QhSd6UxzfdPypovxZMuzvgt43Bgp9 jKdAiUUCQlpxIO9TUh3yo1LnyA+3SasS9tI+/2+gUXa92IU4Xs3enBfDXuQEUBEmROIo7ih1wyjP5 zFsblMu0+t089C+Y0f+hwJM54MsFyTDh6h3YPY8KTbMBKicD7ofXP7qaQnKRgMgW4adLVzZSppQST STJsLkcLg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX5se-00071Z-Qm; Mon, 26 Oct 2020 17:02:00 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kX5sb-000708-FX for linux-arm-kernel@lists.infradead.org; Mon, 26 Oct 2020 17:01:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 14F6B11FB; Mon, 26 Oct 2020 10:01:56 -0700 (PDT) Received: from C02TD0UTHF1T.local (unknown [10.57.56.187]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id EE0E73F719; Mon, 26 Oct 2020 10:01:53 -0700 (PDT) Date: Mon, 26 Oct 2020 17:01:51 +0000 From: Mark Rutland To: Arnd Bergmann Subject: Re: [PATCH 3/4] arm64: avoid -Woverride-init warning Message-ID: <20201026170151.GB42952@C02TD0UTHF1T.local> References: <20201026160342.3705327-1-arnd@kernel.org> <20201026160342.3705327-3-arnd@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201026160342.3705327-3-arnd@kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201026_130157_757946_69E3E818 X-CRM114-Status: GOOD ( 26.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-kernel@vger.kernel.org, Arnd Bergmann , Anshuman Khandual , Catalin Marinas , Suzuki K Poulose , Will Deacon , "Gustavo A. R. Silva" , Steven Price , James Morse , Marc Zyngier , Vincenzo Frascino , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Oct 26, 2020 at 05:03:30PM +0100, Arnd Bergmann wrote: > From: Arnd Bergmann > > The icache_policy_str[] definition causes a warning when extra > warning flags are enabled: > > arch/arm64/kernel/cpuinfo.c:38:26: warning: initialized field overwritten [-Woverride-init] > 38 | [ICACHE_POLICY_VIPT] = "VIPT", > | ^~~~~~ > arch/arm64/kernel/cpuinfo.c:38:26: note: (near initialization for 'icache_policy_str[2]') > arch/arm64/kernel/cpuinfo.c:39:26: warning: initialized field overwritten [-Woverride-init] > 39 | [ICACHE_POLICY_PIPT] = "PIPT", > | ^~~~~~ > arch/arm64/kernel/cpuinfo.c:39:26: note: (near initialization for 'icache_policy_str[3]') > arch/arm64/kernel/cpuinfo.c:40:27: warning: initialized field overwritten [-Woverride-init] > 40 | [ICACHE_POLICY_VPIPT] = "VPIPT", > | ^~~~~~~ > arch/arm64/kernel/cpuinfo.c:40:27: note: (near initialization for 'icache_policy_str[0]') > > There is no real need for the default initializer here, as printing a > NULL string is harmless. Rewrite the logic to have an explicit > reserved value for the only one that uses the default value. > > This partially reverts the commit that removed ICACHE_POLICY_AIVIVT. > > Fixes: 155433cb365e ("arm64: cache: Remove support for ASID-tagged VIVT I-caches") > Signed-off-by: Arnd Bergmann > --- > arch/arm64/include/asm/cache.h | 1 + > arch/arm64/kernel/cpuinfo.c | 5 +++-- > 2 files changed, 4 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/cache.h b/arch/arm64/include/asm/cache.h > index a4d1b5f771f6..16e1e16e7e61 100644 > --- a/arch/arm64/include/asm/cache.h > +++ b/arch/arm64/include/asm/cache.h > @@ -24,6 +24,7 @@ > #define CTR_L1IP(ctr) (((ctr) >> CTR_L1IP_SHIFT) & CTR_L1IP_MASK) > > #define ICACHE_POLICY_VPIPT 0 > +#define ICACHE_POLICY_RESERVED 1 > #define ICACHE_POLICY_VIPT 2 > #define ICACHE_POLICY_PIPT 3 > > diff --git a/arch/arm64/kernel/cpuinfo.c b/arch/arm64/kernel/cpuinfo.c > index 6a7bb3729d60..b63269c7fcdb 100644 > --- a/arch/arm64/kernel/cpuinfo.c > +++ b/arch/arm64/kernel/cpuinfo.c > @@ -34,10 +34,10 @@ DEFINE_PER_CPU(struct cpuinfo_arm64, cpu_data); > static struct cpuinfo_arm64 boot_cpu_data; > > static const char *icache_policy_str[] = { > - [0 ... ICACHE_POLICY_PIPT] = "RESERVED/UNKNOWN", > + [ICACHE_POLICY_VPIPT] = "VPIPT", > + [ICACHE_POLICY_RESERVED] = "RESERVED/UNKNOWN", > [ICACHE_POLICY_VIPT] = "VIPT", > [ICACHE_POLICY_PIPT] = "PIPT", > - [ICACHE_POLICY_VPIPT] = "VPIPT", > }; Given it's not clear that ICACHE_POLICY_PIPT is the max value, I agree this is a bit cleaner. I don't have a nicer way of making this clearer. [...] > @@ -335,6 +335,7 @@ static void cpuinfo_detect_icache_policy(struct cpuinfo_arm64 *info) > set_bit(ICACHEF_VPIPT, &__icache_flags); > break; > default: > + case ICACHE_POLICY_RESERVED: > case ICACHE_POLICY_VIPT: > /* Assume aliasing */ > set_bit(ICACHEF_ALIASING, &__icache_flags); > ... but it's a bit weird to have both the default and ICACHE_POLICY_RESERVED cases. If we get rid of the default case, does any compiler warn? I suspect the masking in CTR_L1IP() might be sufficient to let the compiler see we've handled all cases. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel