Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL

[Russell King - ARM Linux admin <linux@armlinux.org.uk>]

On Tue, Oct 27, 2020 at 03:45:12PM +0800, Miles Chen wrote:
> On Fri, 2020-10-23 at 11:08 +0100, Russell King - ARM Linux admin wrote:
> > On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote:
> > > From: Minchan Kim <minchan@kernel.org>
> > > 
> > > This patch introduces L_PTE_SPECIAL and pte functions for supporting
> > > get_user_pages_fast.
> > > 
> > > Cc: Russell King <linux@armlinux.org.uk>
> > > Cc: Catalin Marinas <catalin.marinas@arm.com>
> > > Cc: Will Deacon <will.deacon@arm.com>
> > > Cc: Steve Capper <steve.capper@linaro.org>
> > > Cc: Minchan Kim <minchan@kernel.org>
> > > Cc: Suren Baghdasaryan <surenb@google.com>
> > > Signed-off-by: Minchan Kim <minchan@kernel.org>
> > > Signed-off-by: Miles Chen <miles.chen@mediatek.com>
> > > ---
> > >  arch/arm/Kconfig                      |  4 ++--
> > >  arch/arm/include/asm/pgtable-2level.h |  1 +
> > >  arch/arm/include/asm/pgtable-3level.h |  6 ------
> > >  arch/arm/include/asm/pgtable.h        | 13 +++++++++++++
> > >  4 files changed, 16 insertions(+), 8 deletions(-)
> > > 
> > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig
> > > index c18fa9d382b7..1f75864b7c7a 100644
> > > --- a/arch/arm/Kconfig
> > > +++ b/arch/arm/Kconfig
> > > @@ -13,7 +13,7 @@ config ARM
> > >  	select ARCH_HAS_KCOV
> > >  	select ARCH_HAS_MEMBARRIER_SYNC_CORE
> > >  	select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE
> > > -	select ARCH_HAS_PTE_SPECIAL if ARM_LPAE
> > > +	select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > >  	select ARCH_HAS_PHYS_TO_DMA
> > >  	select ARCH_HAS_SETUP_DMA_OPS
> > >  	select ARCH_HAS_SET_MEMORY
> > > @@ -82,7 +82,7 @@ config ARM
> > >  	select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE
> > >  	select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU
> > >  	select HAVE_EXIT_THREAD
> > > -	select HAVE_FAST_GUP if ARM_LPAE
> > > +	select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K)
> > >  	select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL
> > >  	select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG
> > >  	select HAVE_FUNCTION_TRACER if !XIP_KERNEL
> > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h
> > > index cdcd55cca37d..385e7a32394e 100644
> > > --- a/arch/arm/include/asm/pgtable-2level.h
> > > +++ b/arch/arm/include/asm/pgtable-2level.h
> > > @@ -117,6 +117,7 @@
> > >  #define L_PTE_VALID		(_AT(pteval_t, 1) << 0)		/* Valid */
> > >  #define L_PTE_PRESENT		(_AT(pteval_t, 1) << 0)
> > >  #define L_PTE_YOUNG		(_AT(pteval_t, 1) << 1)
> > > +#define L_PTE_SPECIAL		(_AT(pteval_t, 1) << 5)
> > 
> > How does this work?  Bits 2 through 5 are already in use for the memory
> > type.
> > 
> > Repurposing this bit means that L_PTE_MT_DEV_NONSHARED,
> > L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with
> > it.
> 
> Thanks for the comment.
> The idea is to re-order the memory type table in [1] (patch v2/4) and
> use bit 5 for L_PTE_SPECIAL.

Thanks, I know what you are trying to achieve. I don't think it's
possible without breaking the kernel on some CPUs and configurations.

-- 
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