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Received: from shell.armlinux.org.uk ([fd8f:7570:feb6:1:5054:ff:fe00:4ec]:51558) by pandora.armlinux.org.uk with esmtpsa (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kXL1G-0000eI-Q1; Tue, 27 Oct 2020 09:11:54 +0000 Received: from linux by shell.armlinux.org.uk with local (Exim 4.92) (envelope-from ) id 1kXL1D-0003tx-Af; Tue, 27 Oct 2020 09:11:51 +0000 Date: Tue, 27 Oct 2020 09:11:51 +0000 From: Russell King - ARM Linux admin To: Miles Chen Subject: Re: [PATCH v2 3/4] arm: mm: introduce L_PTE_SPECIAL Message-ID: <20201027091151.GK1551@shell.armlinux.org.uk> References: <20201023091437.8225-1-miles.chen@mediatek.com> <20201023091437.8225-4-miles.chen@mediatek.com> <20201023100810.GY1551@shell.armlinux.org.uk> <1603784712.12492.5.camel@mtkswgap22> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1603784712.12492.5.camel@mtkswgap22> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201027_051203_337848_01EFE648 X-CRM114-Status: GOOD ( 25.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Steve Capper , wsd_upstream@mediatek.com, Catalin Marinas , Will Deacon , linux-kernel@vger.kernel.org, Minchan Kim , linux-mediatek@lists.infradead.org, Suren Baghdasaryan , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Oct 27, 2020 at 03:45:12PM +0800, Miles Chen wrote: > On Fri, 2020-10-23 at 11:08 +0100, Russell King - ARM Linux admin wrote: > > On Fri, Oct 23, 2020 at 05:14:36PM +0800, Miles Chen wrote: > > > From: Minchan Kim > > > > > > This patch introduces L_PTE_SPECIAL and pte functions for supporting > > > get_user_pages_fast. > > > > > > Cc: Russell King > > > Cc: Catalin Marinas > > > Cc: Will Deacon > > > Cc: Steve Capper > > > Cc: Minchan Kim > > > Cc: Suren Baghdasaryan > > > Signed-off-by: Minchan Kim > > > Signed-off-by: Miles Chen > > > --- > > > arch/arm/Kconfig | 4 ++-- > > > arch/arm/include/asm/pgtable-2level.h | 1 + > > > arch/arm/include/asm/pgtable-3level.h | 6 ------ > > > arch/arm/include/asm/pgtable.h | 13 +++++++++++++ > > > 4 files changed, 16 insertions(+), 8 deletions(-) > > > > > > diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig > > > index c18fa9d382b7..1f75864b7c7a 100644 > > > --- a/arch/arm/Kconfig > > > +++ b/arch/arm/Kconfig > > > @@ -13,7 +13,7 @@ config ARM > > > select ARCH_HAS_KCOV > > > select ARCH_HAS_MEMBARRIER_SYNC_CORE > > > select ARCH_HAS_NON_OVERLAPPING_ADDRESS_SPACE > > > - select ARCH_HAS_PTE_SPECIAL if ARM_LPAE > > > + select ARCH_HAS_PTE_SPECIAL if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K) > > > select ARCH_HAS_PHYS_TO_DMA > > > select ARCH_HAS_SETUP_DMA_OPS > > > select ARCH_HAS_SET_MEMORY > > > @@ -82,7 +82,7 @@ config ARM > > > select HAVE_DYNAMIC_FTRACE_WITH_REGS if HAVE_DYNAMIC_FTRACE > > > select HAVE_EFFICIENT_UNALIGNED_ACCESS if (CPU_V6 || CPU_V6K || CPU_V7) && MMU > > > select HAVE_EXIT_THREAD > > > - select HAVE_FAST_GUP if ARM_LPAE > > > + select HAVE_FAST_GUP if (ARM_LPAE || CPU_V7 || CPU_V6 || CPUV6K) > > > select HAVE_FTRACE_MCOUNT_RECORD if !XIP_KERNEL > > > select HAVE_FUNCTION_GRAPH_TRACER if !THUMB2_KERNEL && !CC_IS_CLANG > > > select HAVE_FUNCTION_TRACER if !XIP_KERNEL > > > diff --git a/arch/arm/include/asm/pgtable-2level.h b/arch/arm/include/asm/pgtable-2level.h > > > index cdcd55cca37d..385e7a32394e 100644 > > > --- a/arch/arm/include/asm/pgtable-2level.h > > > +++ b/arch/arm/include/asm/pgtable-2level.h > > > @@ -117,6 +117,7 @@ > > > #define L_PTE_VALID (_AT(pteval_t, 1) << 0) /* Valid */ > > > #define L_PTE_PRESENT (_AT(pteval_t, 1) << 0) > > > #define L_PTE_YOUNG (_AT(pteval_t, 1) << 1) > > > +#define L_PTE_SPECIAL (_AT(pteval_t, 1) << 5) > > > > How does this work? Bits 2 through 5 are already in use for the memory > > type. > > > > Repurposing this bit means that L_PTE_MT_DEV_NONSHARED, > > L_PTE_MT_DEV_WC, L_PTE_MT_DEV_CACHED and L_PTE_MT_VECTORS clash with > > it. > > Thanks for the comment. > The idea is to re-order the memory type table in [1] (patch v2/4) and > use bit 5 for L_PTE_SPECIAL. Thanks, I know what you are trying to achieve. I don't think it's possible without breaking the kernel on some CPUs and configurations. -- RMK's Patch system: https://www.armlinux.org.uk/developer/patches/ FTTP is here! 40Mbps down 10Mbps up. Decent connectivity at last! _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel