From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-11.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 33EA2C4363A for ; Wed, 28 Oct 2020 10:16:37 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 8BD812222C for ; Wed, 28 Oct 2020 10:16:36 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="xwZDQqfx" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8BD812222C Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=s9AQdrfyO/BPSOgiEekwlUIRRRSMrCAl8tAvKhelMYA=; b=xwZDQqfxQcV6vSXEmRVwPmE/R CvxRCAPcxcd/tnt6UWfj8KLy8c+RI4Q2cLxDqB149GT990sMbXWUhZrKvtF8l0BK9LiEe3pEAKVXx b2ianyc+obrdF7p+zlxqssqc9H/SwZU48mneIvIUxETKOYLRpIZdclSrrO8uovNOFAkR3nsPrAzUZ k5jiiCT23IoJjWlcgp+eC3sf9WyatM3HLC3W1t5xisiv1KzP0mjXuYEtqNkVUYZgMdc7PaeK1XjCy cgW3PSlIELCg2JXoI37uAjpVmAghSPHZfLJetK3H2zpkKrcT8ETzCz6XmirY4uuCJvBG4BGpxAmMY LUv94vCTw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXiUu-0006Go-VE; Wed, 28 Oct 2020 10:16:05 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kXiUs-0006G5-87 for linux-arm-kernel@lists.infradead.org; Wed, 28 Oct 2020 10:16:02 +0000 Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kXiUj-0002Qk-8m; Wed, 28 Oct 2020 11:15:53 +0100 Received: from sha by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1kXiUi-0000Xa-FY; Wed, 28 Oct 2020 11:15:52 +0100 Date: Wed, 28 Oct 2020 11:15:52 +0100 From: Sascha Hauer To: Abel Vesa Subject: Re: [PATCH] clk: imx: gate2: Fix the is_enabled op Message-ID: <20201028101552.GA26805@pengutronix.de> References: <1603738248-8193-1-git-send-email-abel.vesa@nxp.com> <20201028082412.GU26805@pengutronix.de> <20201028095057.cuaxqqr4yzxvzwvp@fsr-ub1664-175> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201028095057.cuaxqqr4yzxvzwvp@fsr-ub1664-175> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 11:04:33 up 251 days, 17:35, 155 users, load average: 0.06, 0.22, 0.24 User-Agent: Mutt/1.10.1 (2018-07-13) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201028_061602_307825_47F3DCFB X-CRM114-Status: GOOD ( 28.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Dong Aisheng , Rob Herring , Peng Fan , Jacky Bai , Anson Huang , Stephen Boyd , Mike Turquette , Linux Kernel Mailing List , NXP Linux Team , Sascha Hauer , Fabio Estevam , Shawn Guo , linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Oct 28, 2020 at 11:50:57AM +0200, Abel Vesa wrote: > On 20-10-28 09:24:12, Sascha Hauer wrote: > > Hi Abel, > > > > On Mon, Oct 26, 2020 at 08:50:48PM +0200, Abel Vesa wrote: > > > The clock is considered to be enabled only if the controlling bits > > > match the cgr_val mask. Also make sure the is_enabled returns the > > > correct vaule by locking the access to the register. > > > > > > Signed-off-by: Abel Vesa > > > Fixes: 1e54afe9fcfe ("clk: imx: gate2: Allow single bit gating clock") > > > --- > > > drivers/clk/imx/clk-gate2.c | 60 ++++++++++++++++++++------------------------- > > > drivers/clk/imx/clk.h | 8 ++---- > > > 2 files changed, 29 insertions(+), 39 deletions(-) > > > > > > diff --git a/drivers/clk/imx/clk-gate2.c b/drivers/clk/imx/clk-gate2.c > > > index 7eed708..f320bd2b 100644 > > > --- a/drivers/clk/imx/clk-gate2.c > > > +++ b/drivers/clk/imx/clk-gate2.c > > > @@ -37,10 +37,22 @@ struct clk_gate2 { > > > > > > #define to_clk_gate2(_hw) container_of(_hw, struct clk_gate2, hw) > > > > > > +static void clk_gate2_do_shared_clks(struct clk_hw *hw, bool enable) > > > +{ > > > + struct clk_gate2 *gate = to_clk_gate2(hw); > > > + u32 reg; > > > + > > > + reg = readl(gate->reg); > > > + if (enable) > > > + reg |= gate->cgr_val << gate->bit_idx; > > > + else > > > + reg &= ~(gate->cgr_val << gate->bit_idx); > > > > Shouldn't this be: > > > > reg &= ~(3 << gate->bit_idx); > > if (enable) > > reg |= gate->cgr_val << gate->bit_idx; > > > > At least that's how it was without this patch and that's how it makes > > sense to me with cgr_val != 3. > > > > Well, that's the actual problem. The value 3 forces all the clocks > that register with this clock type to have 2 bits for controlling the gate. > > My patch (though now I think I should split it into 2 separate patches) allows > two HW gates to be controlled by as many bits necessary. For example, there > could be multiple HW gates that are controled by the same bit. By passing > the cgr_val when registering the clocks you can specify how many bits (as a mask) > control all those HW gates that share their control bits. cgr_val is not a mask, it's a value that shall be written to the two bits to enable the clock. cgr_val could also be 0b10, see imx_clk_gate2_cgr(). Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel