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[209.6.122.159]) by smtp.gmail.com with ESMTPSA id i18sm8187020qtv.38.2020.11.02.08.17.07 (version=TLS1_2 cipher=ECDHE-ECDSA-CHACHA20-POLY1305 bits=256/256); Mon, 02 Nov 2020 08:17:08 -0800 (PST) Date: Mon, 2 Nov 2020 11:17:06 -0500 From: Masayoshi Mizuma To: Sumit Garg Subject: Re: [PATCH v7 2/7] irqchip/gic-v3: Enable support for SGIs to act as NMIs Message-ID: <20201102161706.xfqdsro7q7k65ybb@gabell> References: <1604317487-14543-1-git-send-email-sumit.garg@linaro.org> <1604317487-14543-3-git-send-email-sumit.garg@linaro.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1604317487-14543-3-git-send-email-sumit.garg@linaro.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201102_111714_355771_3D02BA9F X-CRM114-Status: GOOD ( 22.17 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: mark.rutland@arm.com, daniel.thompson@linaro.org, tsbogend@alpha.franken.de, linux-kernel@vger.kernel.org, jason@lakedaemon.net, ito-yuichi@fujitsu.com, maz@kernel.org, x86@kernel.org, linux@armlinux.org.uk, dianders@chromium.org, jason.wessel@windriver.com, mingo@redhat.com, bp@alien8.de, mpe@ellerman.id.au, catalin.marinas@arm.com, kgdb-bugreport@lists.sourceforge.net, tglx@linutronix.de, julien.thierry.kdev@gmail.com, will@kernel.org, davem@davemloft.net, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 02, 2020 at 05:14:42PM +0530, Sumit Garg wrote: > Add support to handle SGIs as pseudo NMIs. As SGIs or IPIs default to a > special flow handler: handle_percpu_devid_fasteoi_ipi(), so skip NMI > handler update in case of SGIs. > > Also, enable NMI support prior to gic_smp_init() as allocation of SGIs > as IRQs/NMIs happen as part of this routine. > > Signed-off-by: Sumit Garg > --- > drivers/irqchip/irq-gic-v3.c | 29 +++++++++++++++++++++-------- > 1 file changed, 21 insertions(+), 8 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 16fecc0..7010ae2 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -461,6 +461,7 @@ static u32 gic_get_ppi_index(struct irq_data *d) > static int gic_irq_nmi_setup(struct irq_data *d) > { > struct irq_desc *desc = irq_to_desc(d->irq); > + u32 idx; > > if (!gic_supports_nmi()) > return -EINVAL; > @@ -478,16 +479,22 @@ static int gic_irq_nmi_setup(struct irq_data *d) > return -EINVAL; > > /* desc lock should already be held */ > - if (gic_irq_in_rdist(d)) { > - u32 idx = gic_get_ppi_index(d); > + switch (get_intid_range(d)) { > + case SGI_RANGE: > + break; > + case PPI_RANGE: > + case EPPI_RANGE: > + idx = gic_get_ppi_index(d); > > /* Setting up PPI as NMI, only switch handler for first NMI */ > if (!refcount_inc_not_zero(&ppi_nmi_refs[idx])) { > refcount_set(&ppi_nmi_refs[idx], 1); > desc->handle_irq = handle_percpu_devid_fasteoi_nmi; > } > - } else { > + break; > + default: > desc->handle_irq = handle_fasteoi_nmi; > + break; > } > > gic_irq_set_prio(d, GICD_INT_NMI_PRI); > @@ -498,6 +505,7 @@ static int gic_irq_nmi_setup(struct irq_data *d) > static void gic_irq_nmi_teardown(struct irq_data *d) > { > struct irq_desc *desc = irq_to_desc(d->irq); > + u32 idx; > > if (WARN_ON(!gic_supports_nmi())) > return; > @@ -515,14 +523,20 @@ static void gic_irq_nmi_teardown(struct irq_data *d) > return; > > /* desc lock should already be held */ > - if (gic_irq_in_rdist(d)) { > - u32 idx = gic_get_ppi_index(d); > + switch (get_intid_range(d)) { > + case SGI_RANGE: > + break; > + case PPI_RANGE: > + case EPPI_RANGE: > + idx = gic_get_ppi_index(d); > > /* Tearing down NMI, only switch handler for last NMI */ > if (refcount_dec_and_test(&ppi_nmi_refs[idx])) > desc->handle_irq = handle_percpu_devid_irq; > - } else { > + break; > + default: > desc->handle_irq = handle_fasteoi_irq; > + break; > } > > gic_irq_set_prio(d, GICD_INT_DEF_PRI); > @@ -1708,6 +1722,7 @@ static int __init gic_init_bases(void __iomem *dist_base, > > gic_dist_init(); > gic_cpu_init(); > + gic_enable_nmi_support(); > gic_smp_init(); > gic_cpu_pm_init(); > > @@ -1719,8 +1734,6 @@ static int __init gic_init_bases(void __iomem *dist_base, > gicv2m_init(handle, gic_data.domain); > } > > - gic_enable_nmi_support(); > - > return 0; > > out_free: > -- Looks good to me. Please feel free to add: Reviewed-by: Masayoshi Mizuma Thanks! Masa _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel