Re: [PATCH] arm64: dts: ti: k3-am65: mark dss as dma-coherent

From: Nishanth Menon <nm@ti.com>
To: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>,
	devicetree@vger.kernel.org, Robin Murphy <robin.murphy@arm.com>,
	Nikhil Devshatwar <nikhil.nd@ti.com>,
	linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH] arm64: dts: ti: k3-am65: mark dss as dma-coherent
Date: Mon, 2 Nov 2020 10:46:49 -0600	[thread overview]
Message-ID: <20201102164649.npl22f27psrwbxzo@outwit> (raw)
In-Reply-To: <4998118a-f8ec-fc8c-2535-729bb0b68ec9@ti.com>

On 15:42-20201102, Tomi Valkeinen wrote:
> Hi,
> 
> On 02/11/2020 15:01, Robin Murphy wrote:
> > On 2020-10-30 14:08, Tomi Valkeinen wrote:
> >> On 29/10/2020 16:52, Nishanth Menon wrote:
> >>> On 20:11-20201029, Nikhil Devshatwar wrote:
> >>>> On 16:11-20201029, Tomi Valkeinen wrote:
> >>>>> DSS is IO coherent on AM65, so we can mark it as such with
> >>>>> 'dma-coherent' property in the DT file.
> >>>>>
> >>>>> Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
> >>>> Acked-by: Nikhil Devshatwar <nikhil.nd@ti.com>
> >>>>
> >>>
> >>> Tomi: Do you need to add Fixes: tag to percolate this to stable? if
> >>> yes, please comment, makes it easier for me to queue for 5.10 if
> >>> possible
> >>
> >> I don't see this as a fix, but an optimization. Nothing is broken without this.
> > 
> > Note that if the driver doesn't have explicit control over what type of memory access the device
> > makes, that's not necessarily true.
> > 
> > If coherent DMA buffers are allocated from regular kernel memory, there's still a cacheable alias
> > kicking around that can be speculatively fetched into a cache somewhere. If the device is genuinely
> > non-coherent, or configured to make non-snooping accesses, then that's not an issue, but it it's
> > hard-wired to make snooping accesses it can start hitting that cached alias and not see subsequent
> > updates to the buffer, since those are written straight to RAM via the non-cacheable mapping. At
> > that point it becomes an actual problem (and it's not just theoretical - we've hit a real-world
> > example of this recently with GPUs on certain Amlogic devices).
> 
> Ok, thanks. I don't know if that the case here, but better safe than sorry. I'll send a new one with
> appropriate tags.

Yes - the default AM65 MAT tables do force a snoop into the clusters
when using DDR based buffers. Deal with display is when you dont get to
see the artifacts unless you are closely monitoring frame by frame and
transitions.. which in the middle of all other automatic backend cache
operations tends to be rather something easy to miss..

Will let the next rev cook for a few days unless folks have some
additional comments..

-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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