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Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaj5w-0004vH-13; Thu, 05 Nov 2020 17:30:44 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kaj5t-0004uF-NG for linux-arm-kernel@lists.infradead.org; Thu, 05 Nov 2020 17:30:42 +0000 Received: from gaia (unknown [2.26.170.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 5C3DF206B6; Thu, 5 Nov 2020 17:30:37 +0000 (UTC) Date: Thu, 5 Nov 2020 17:30:34 +0000 From: Catalin Marinas To: Andrey Konovalov Subject: Re: [PATCH v8 32/43] arm64: mte: Switch GCR_EL1 in kernel entry and exit Message-ID: <20201105173033.GF30030@gaia> References: <5d9ece04df8e9d60e347a2f6f96b8c52316bfe66.1604531793.git.andreyknvl@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <5d9ece04df8e9d60e347a2f6f96b8c52316bfe66.1604531793.git.andreyknvl@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201105_123041_858575_233181C2 X-CRM114-Status: GOOD ( 18.45 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-kernel@lists.infradead.org, Marco Elver , Kevin Brodsky , Will Deacon , Branislav Rankov , kasan-dev@googlegroups.com, linux-kernel@vger.kernel.org, linux-mm@kvack.org, Alexander Potapenko , Evgenii Stepanov , Andrey Ryabinin , Andrew Morton , Vincenzo Frascino , Dmitry Vyukov Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 05, 2020 at 12:18:47AM +0100, Andrey Konovalov wrote: > diff --git a/arch/arm64/kernel/mte.c b/arch/arm64/kernel/mte.c > index 14b0c19a33e3..cc7e0f8707f7 100644 > --- a/arch/arm64/kernel/mte.c > +++ b/arch/arm64/kernel/mte.c > @@ -23,6 +23,8 @@ > #include > #include > > +u64 gcr_kernel_excl __ro_after_init; > + > static void mte_sync_page_tags(struct page *page, pte_t *ptep, bool check_swap) > { > pte_t old_pte = READ_ONCE(*ptep); > @@ -123,6 +125,23 @@ void *mte_set_mem_tag_range(void *addr, size_t size, u8 tag) > > void __init mte_init_tags(u64 max_tag) > { > + static bool gcr_kernel_excl_initialized = false; > + > + if (!gcr_kernel_excl_initialized) { > + /* > + * The format of the tags in KASAN is 0xFF and in MTE is 0xF. > + * This conversion extracts an MTE tag from a KASAN tag. > + */ > + u64 incl = GENMASK(FIELD_GET(MTE_TAG_MASK >> MTE_TAG_SHIFT, > + max_tag), 0); > + > + gcr_kernel_excl = ~incl & SYS_GCR_EL1_EXCL_MASK; > + gcr_kernel_excl_initialized = true; > + } > + > + /* Enable the kernel exclude mask for random tags generation. */ > + write_sysreg_s(SYS_GCR_EL1_RRND | gcr_kernel_excl, SYS_GCR_EL1); Same question as on a previous patch. Is SYS_GCR_EL1 written on the other registers via cpu_enable_mte()? -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel