From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v3 16/26] coresight: etm4x: Check for Software Lock
Date: Thu, 5 Nov 2020 14:50:00 -0700 [thread overview]
Message-ID: <20201105215000.GB3047244@xps15> (raw)
In-Reply-To: <20201028220945.3826358-18-suzuki.poulose@arm.com>
On Wed, Oct 28, 2020 at 10:09:35PM +0000, Suzuki K Poulose wrote:
> The Software lock is not implemented for system instructions
> based accesses. So, skip the lock register access in such
> cases.
>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> .../coresight/coresight-etm4x-core.c | 40 ++++++++++++-------
> 1 file changed, 25 insertions(+), 15 deletions(-)
>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index a5c914b16e59..a12d58a04c5d 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -121,6 +121,21 @@ static void etm4_os_lock(struct etmv4_drvdata *drvdata)
> isb();
> }
>
> +static void etm4_cs_lock(struct etmv4_drvdata *drvdata,
> + struct csdev_access *csa)
> +{
> + /* Software Lock is only accessible via memory mapped interface */
> + if (csa->io_mem)
> + CS_LOCK(csa->base);
> +}
> +
> +static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
> + struct csdev_access *csa)
> +{
> + if (csa->io_mem)
> + CS_UNLOCK(csa->base);
> +}
> +
> static bool etm4_arch_supported(u8 arch)
> {
> /* Mask out the minor version number */
> @@ -160,8 +175,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> struct device *etm_dev = &csdev->dev;
> struct csdev_access *csa = &csdev->access;
>
> - CS_UNLOCK(drvdata->base);
> -
> + etm4_cs_unlock(drvdata, csa);
> etm4_os_unlock(drvdata);
>
> rc = coresight_claim_device_unlocked(csdev);
> @@ -262,7 +276,7 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
> isb();
>
> done:
> - CS_LOCK(drvdata->base);
> + etm4_cs_lock(drvdata, csa);
>
> dev_dbg(etm_dev, "cpu: %d enable smp call done: %d\n",
> drvdata->cpu, rc);
> @@ -519,7 +533,7 @@ static void etm4_disable_hw(void *info)
> struct csdev_access *csa = &csdev->access;
> int i;
>
> - CS_UNLOCK(drvdata->base);
> + etm4_cs_unlock(drvdata, csa);
>
> if (!drvdata->skip_power_up) {
> /* power can be removed from the trace unit now */
> @@ -560,8 +574,7 @@ static void etm4_disable_hw(void *info)
> }
>
> coresight_disclaim_device_unlocked(csdev);
> -
> - CS_LOCK(drvdata->base);
> + etm4_cs_lock(drvdata, csa);
>
> dev_dbg(&drvdata->csdev->dev,
> "cpu: %d disable smp call done\n", drvdata->cpu);
> @@ -671,8 +684,7 @@ static void etm4_init_arch_data(void *info)
>
> /* Make sure all registers are accessible */
> etm4_os_unlock_csa(drvdata, csa);
> -
> - CS_UNLOCK(drvdata->base);
> + etm4_cs_unlock(drvdata, csa);
>
> /* find all capabilities of the tracing unit */
> etmidr0 = etm4x_relaxed_read32(csa, TRCIDR0);
> @@ -837,7 +849,7 @@ static void etm4_init_arch_data(void *info)
> drvdata->nrseqstate = BMVAL(etmidr5, 25, 27);
> /* NUMCNTR, bits[30:28] number of counters available for tracing */
> drvdata->nr_cntr = BMVAL(etmidr5, 28, 30);
> - CS_LOCK(drvdata->base);
> + etm4_cs_lock(drvdata, csa);
> }
>
> /* Set ELx trace filter access in the TRCVICTLR register */
> @@ -1218,8 +1230,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> dsb(sy);
> isb();
>
> - CS_UNLOCK(drvdata->base);
> -
> + etm4_cs_unlock(drvdata, csa);
> /* Lock the OS lock to disable trace and external debugger access */
> etm4_os_lock(drvdata);
>
> @@ -1330,7 +1341,7 @@ static int etm4_cpu_save(struct etmv4_drvdata *drvdata)
> etm4x_relaxed_write32(csa, (state->trcpdcr & ~TRCPDCR_PU), TRCPDCR);
>
> out:
> - CS_LOCK(drvdata->base);
> + etm4_cs_lock(drvdata, csa);
> return ret;
> }
>
> @@ -1341,8 +1352,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
> struct csdev_access tmp_csa = CSDEV_ACCESS_IOMEM(drvdata->base);
> struct csdev_access *csa = &tmp_csa;
>
> - CS_UNLOCK(drvdata->base);
> -
> + etm4_cs_unlock(drvdata, csa);
> etm4x_relaxed_write32(csa, state->trcclaimset, TRCCLAIMSET);
>
> etm4x_relaxed_write32(csa, state->trcprgctlr, TRCPRGCTLR);
> @@ -1426,7 +1436,7 @@ static void etm4_cpu_restore(struct etmv4_drvdata *drvdata)
>
> /* Unlock the OS lock to re-enable trace and external debug access */
> etm4_os_unlock(drvdata);
> - CS_LOCK(drvdata->base);
> + etm4_cs_lock(drvdata, csa);
> }
>
> static int etm4_cpu_pm_notify(struct notifier_block *nb, unsigned long cmd,
> --
> 2.24.1
>
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next prev parent reply other threads:[~2020-11-05 21:50 UTC|newest]
Thread overview: 77+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-02 21:46 ` Mathieu Poirier
2020-11-02 22:04 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-03 17:14 ` Mathieu Poirier
2020-11-03 17:25 ` Mathieu Poirier
2020-11-04 10:07 ` Suzuki K Poulose
2020-11-09 21:00 ` Mathieu Poirier
2020-11-10 9:24 ` Suzuki K Poulose
2020-11-10 17:02 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-03 18:03 ` Mathieu Poirier
2020-11-04 10:42 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-03 18:36 ` Mathieu Poirier
2020-11-04 10:54 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-03 18:53 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-03 19:03 ` Mathieu Poirier
2020-11-03 19:04 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-10-29 15:26 ` Suzuki K Poulose
2020-11-05 20:52 ` Mathieu Poirier
2020-11-05 22:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-05 21:50 ` Mathieu Poirier [this message]
2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-05 21:55 ` Mathieu Poirier
2020-11-09 9:40 ` Suzuki K Poulose
2020-11-09 17:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-06 18:52 ` Mathieu Poirier
2020-11-09 9:44 ` Suzuki K Poulose
2020-11-10 23:15 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-06 20:34 ` Mathieu Poirier
2020-11-09 9:48 ` Suzuki K Poulose
2020-11-09 17:48 ` Mathieu Poirier
2020-11-06 20:46 ` Mathieu Poirier
2020-11-10 10:47 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-06 21:11 ` Mathieu Poirier
2020-11-09 9:51 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-06 21:42 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-09 18:32 ` Mathieu Poirier
2020-11-10 10:11 ` Suzuki K Poulose
2020-11-10 11:40 ` John Horley
2020-11-10 17:35 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-09 20:22 ` Mathieu Poirier
2020-11-10 9:31 ` Suzuki K Poulose
2020-11-10 17:33 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-09 20:43 ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-09 20:46 ` Mathieu Poirier
2020-11-10 10:50 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-02 15:31 ` Rob Herring
2020-11-09 20:50 ` Mathieu Poirier
2020-11-10 10:51 ` Suzuki K Poulose
2020-10-29 7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach
2020-10-29 15:45 ` Suzuki K Poulose
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