From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 81585C55179 for ; Fri, 6 Nov 2020 12:44:52 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 0C76F20639 for ; Fri, 6 Nov 2020 12:44:51 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="uYUdv8O3" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 0C76F20639 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=43KkIhjMLJT8l3K3sLjEjpar2sbFbvYmsa5KQfQ4EbM=; b=uYUdv8O3HhlO4DIG8HrXuaJeh OCFykrjdMtGjGiuK7X3JHJPA1kryuWbBLZpvHCPivYDvgckBU6m3AZ0o9LcnqQOkGWsnhRXtPboiF 7OHAb0V+p7EYKDijFCBUdCwwPliwJfhHZwqTkLifOgN2no6WO4ykejUTA1vc3UWFxavcioUBWyFxI iMC8c+Q8LlRP2AzDwCVc6vyvM6Q6SFUUgclNcbUokYvLrIvq18PtNMkiyxzT/JWymcQuAZkGy9sLi I5IvRHUwdZwv49vYQHc4aPghnknRptW9QrJqXw+DRGZXn9/cWba8gozOMC+EORYv6u7brK1u0owyK 8cmQsWGow==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb16D-0005yU-Dz; Fri, 06 Nov 2020 12:44:13 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kb166-0005wE-Bh for linux-arm-kernel@lists.infradead.org; Fri, 06 Nov 2020 12:44:07 +0000 Received: from gaia (unknown [2.26.170.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id CE60120639; Fri, 6 Nov 2020 12:44:03 +0000 (UTC) Date: Fri, 6 Nov 2020 12:44:00 +0000 From: Catalin Marinas To: Suzuki K Poulose Subject: Re: [PATCH] arm64: errata: Fix handling of 1418040 with late CPU onlining Message-ID: <20201106124400.GF29329@gaia> References: <20201106114952.10032-1-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201106_074406_641773_C5EB3E47 X-CRM114-Status: GOOD ( 21.97 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , Sai Prakash Ranjan , Will Deacon , Stephen Boyd , Marc Zyngier , kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 06, 2020 at 12:18:32PM +0000, Suzuki K Poulose wrote: > On 11/6/20 11:49 AM, Will Deacon wrote: > > In a surprising turn of events, it transpires that CPU capabilities > > configured as ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE are never set as the > > result of late-onlining. Therefore our handling of erratum 1418040 does > > not get activated if it is not required by any of the boot CPUs, even > > though we allow late-onlining of an affected CPU. > > The capability state is not altered after the SMP boot for all types > of caps. The weak caps are there to allow a late CPU to turn online > without getting "banned". This may be something we could relax with > a new flag in the scope. Like this? Of course, it needs some testing. diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 97244d4feca9..b896e72131d7 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -246,6 +246,8 @@ extern struct arm64_ftr_reg arm64_ftr_reg_ctrel0; #define ARM64_CPUCAP_OPTIONAL_FOR_LATE_CPU ((u16)BIT(5)) /* Panic when a conflict is detected */ #define ARM64_CPUCAP_PANIC_ON_CONFLICT ((u16)BIT(6)) +/* Together with PERMITTED_FOR_LATE_CPU, set the corresponding cpu_hwcaps bit */ +#define ARM64_CPUCAP_SET_FOR_LATE_CPU ((u16)BIT(7)) /* * CPU errata workarounds that need to be enabled at boot time if one or @@ -481,6 +483,16 @@ static __always_inline bool cpus_have_const_cap(int num) return cpus_have_cap(num); } +/* + * Test for a capability with a runtime check. This is an alias for + * cpus_have_cap() but with the name chosen to emphasize the applicability to + * late capability setting. + */ +static __always_inline bool cpus_have_late_cap(int num) +{ + return cpus_have_cap(num); +} + static inline void cpus_set_cap(unsigned int num) { if (num >= ARM64_NCAPS) { diff --git a/arch/arm64/kernel/cpu_errata.c b/arch/arm64/kernel/cpu_errata.c index 61314fd70f13..6b7de7292e8c 100644 --- a/arch/arm64/kernel/cpu_errata.c +++ b/arch/arm64/kernel/cpu_errata.c @@ -481,7 +481,8 @@ const struct arm64_cpu_capabilities arm64_errata[] = { * also need the non-affected CPUs to be able to come * in at any point in time. Wonderful. */ - .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE | + ARM64_CPUCAP_SET_FOR_LATE_CPU, }, #endif #ifdef CONFIG_ARM64_WORKAROUND_SPECULATIVE_AT diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index dcc165b3fc04..51e63be41ea5 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -1720,6 +1720,12 @@ cpucap_late_cpu_permitted(const struct arm64_cpu_capabilities *cap) return !!(cap->type & ARM64_CPUCAP_PERMITTED_FOR_LATE_CPU); } +static bool +cpucap_set_for_late_cpu(const struct arm64_cpu_capabilities *cap) +{ + return !!(cap->type & ARM64_CPUCAP_SET_FOR_LATE_CPU); +} + static bool cpucap_panic_on_conflict(const struct arm64_cpu_capabilities *cap) { @@ -2489,6 +2495,11 @@ static void verify_local_cpu_caps(u16 scope_mask) */ if (cpu_has_cap && !cpucap_late_cpu_permitted(caps)) break; + /* + * Set the capability bit if it allows late setting. + */ + if (cpucap_set_for_late_cpu(caps)) + cpus_set_cap(caps->capability); } } diff --git a/arch/arm64/kernel/process.c b/arch/arm64/kernel/process.c index 4784011cecac..152639962845 100644 --- a/arch/arm64/kernel/process.c +++ b/arch/arm64/kernel/process.c @@ -523,7 +523,7 @@ static void erratum_1418040_thread_switch(struct task_struct *prev, u64 val; if (!(IS_ENABLED(CONFIG_ARM64_ERRATUM_1418040) && - cpus_have_const_cap(ARM64_WORKAROUND_1418040))) + cpus_have_late_cap(ARM64_WORKAROUND_1418040))) return; prev32 = is_compat_thread(task_thread_info(prev)); _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel