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From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: coresight@lists.linaro.org, linux-kernel@vger.kernel.org,
	linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access
Date: Mon, 9 Nov 2020 11:32:55 -0700	[thread overview]
Message-ID: <20201109183255.GA3396611@xps15> (raw)
In-Reply-To: <20201028220945.3826358-24-suzuki.poulose@arm.com>

On Wed, Oct 28, 2020 at 10:09:41PM +0000, Suzuki K Poulose wrote:
> As per the specification any update to the TRCPRGCTLR must be synchronized
> by a context synchronization event (in our case an explicist ISB) before
> the TRCSTATR is checked.
> 
> Cc: Mike Leach <mike.leach@linaro.org>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
>  drivers/hwtracing/coresight/coresight-etm4x-core.c | 13 +++++++++++++
>  1 file changed, 13 insertions(+)
> 
> diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> index e36bc1c722c7..4bc2f15b6332 100644
> --- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
> +++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
> @@ -178,6 +178,15 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  	/* Disable the trace unit before programming trace registers */
>  	etm4x_relaxed_write32(csa, 0, TRCPRGCTLR);
>  
> +	/*
> +	 * If we use system instructions, we need to synchronize the
> +	 * write to the TRCPRGCTLR, before accessing the TRCSTATR.
> +	 * See ARM IHI0064F, section
> +	 * "4.3.7 Synchronization of register updates"
> +	 */
> +	if (!csa->io_mem)
> +		isb();
> +

When I first read the documentation on system instruction section 4.3.7 really
got me thinking...  

At the very top, right after the title "Synchronization of register updates" one
can read "Software running on the PE...".  Later in the text, when specifying
the synchronisation rules, the term "trace analyzer" is used.  _Typically_ a trace
analyzer is an external box.

Arm documentation is precise and usually doesn't overlook that kind of detail.
The question is to understand if a context synchronisation event is also needed
when programming is done on the PE.  If so I think the documentation should be
amended. 

In that case:

Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>


>  	/* wait for TRCSTATR.IDLE to go up */
>  	if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 1))
>  		dev_err(etm_dev,
> @@ -256,6 +265,10 @@ static int etm4_enable_hw(struct etmv4_drvdata *drvdata)
>  	/* Enable the trace unit */
>  	etm4x_relaxed_write32(csa, 1, TRCPRGCTLR);
>  
> +	/* Synchronize the register updates for sysreg access */
> +	if (!csa->io_mem)
> +		isb();
> +
>  	/* wait for TRCSTATR.IDLE to go back down to '0' */
>  	if (coresight_timeout(csa, TRCSTATR, TRCSTATR_IDLE_BIT, 0))
>  		dev_err(etm_dev,
> -- 
> 2.24.1
> 

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  reply	other threads:[~2020-11-09 18:33 UTC|newest]

Thread overview: 77+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-10-28 22:09 [PATCH v3 00/26] coresight: Support for ETM system instructions Suzuki K Poulose
2020-10-28 22:09 ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 01/26] coresight: etm4x: Fix accesses to TRCVMIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 02/26] coresight: etm4x: Fix accesses to TRCCIDCTLR1 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 03/26] coresight: etm4x: Update TRCIDR3.NUMPROCS handling to match v4.2 Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 04/26] coresight: etm4x: Fix accesses to TRCPROCSELR Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 05/26] coresight: etm4x: Handle TRCVIPCSSCTLR accesses Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 06/26] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-11-02 21:46   ` Mathieu Poirier
2020-11-02 22:04     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 07/26] coresight: Introduce device access abstraction Suzuki K Poulose
2020-11-03 17:14   ` Mathieu Poirier
2020-11-03 17:25     ` Mathieu Poirier
2020-11-04 10:07       ` Suzuki K Poulose
2020-11-09 21:00   ` Mathieu Poirier
2020-11-10  9:24     ` Suzuki K Poulose
2020-11-10 17:02       ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 08/26] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-11-03 18:03   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 09/26] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-11-03 18:03   ` Mathieu Poirier
2020-11-04 10:42     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 10/26] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-11-03 18:36   ` Mathieu Poirier
2020-11-04 10:54     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 11/26] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 12/26] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-11-03 18:53   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 13/26] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-11-03 19:03   ` Mathieu Poirier
2020-11-03 19:04   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 14/26] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-10-29 15:26   ` Suzuki K Poulose
2020-11-05 20:52   ` Mathieu Poirier
2020-11-05 22:47     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 15/26] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 16/26] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-11-05 21:50   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 17/26] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-11-05 21:55   ` Mathieu Poirier
2020-11-09  9:40     ` Suzuki K Poulose
2020-11-09 17:42       ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 18/26] coresight: etm4x: Clean up " Suzuki K Poulose
2020-11-06 18:52   ` Mathieu Poirier
2020-11-09  9:44     ` Suzuki K Poulose
2020-11-10 23:15     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 19/26] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-11-06 20:34   ` Mathieu Poirier
2020-11-09  9:48     ` Suzuki K Poulose
2020-11-09 17:48       ` Mathieu Poirier
2020-11-06 20:46   ` Mathieu Poirier
2020-11-10 10:47     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 20/26] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-11-06 21:11   ` Mathieu Poirier
2020-11-09  9:51     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 21/26] coresight: etm4x: Use TRCDEVARCH for component discovery Suzuki K Poulose
2020-11-06 21:42   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 22/26] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-11-09 18:32   ` Mathieu Poirier [this message]
2020-11-10 10:11     ` Suzuki K Poulose
2020-11-10 11:40       ` John Horley
2020-11-10 17:35       ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 23/26] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-11-09 20:22   ` Mathieu Poirier
2020-11-10  9:31     ` Suzuki K Poulose
2020-11-10 17:33       ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 24/26] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2020-11-09 20:43   ` Mathieu Poirier
2020-10-28 22:09 ` [PATCH v3 25/26] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-11-09 20:46   ` Mathieu Poirier
2020-11-10 10:50     ` Suzuki K Poulose
2020-10-28 22:09 ` [PATCH v3 26/26] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-11-02 15:31   ` Rob Herring
2020-11-09 20:50   ` Mathieu Poirier
2020-11-10 10:51     ` Suzuki K Poulose
2020-10-29  7:53 ` [PATCH v3 00/26] coresight: Support for ETM system instructions Mike Leach
2020-10-29 15:45   ` Suzuki K Poulose

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