From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-9.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id BB5E6C388F9 for ; Wed, 11 Nov 2020 17:05:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 4040F2072C for ; Wed, 11 Nov 2020 17:05:11 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="guCss6fE"; dkim=fail reason="signature verification failed" (2048-bit key) header.d=linaro.org header.i=@linaro.org header.b="WV+GTPvF" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 4040F2072C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=linaro.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=4jOgb5QNGHxtZAP1XHPJtIIXCOgHchXJf93p/4OadZA=; b=guCss6fELVby6iwr6D7YGR0qZ NDiAr489H7nGq8PFos6/dYV18gIdqb0E6Nvzx6RUUARpHICVrOZjeJPaxWLREJEqDNxT+XsZVoSIL hayViz2BmNeA1nVArWtMt9jyWHBGnIq5r2ckYlriyiGWqqx7EmkjWjJvfot/YqBumOwkij9mSJ6Z0 g1sjlUKymKFAxZtupllWU22J0opr9vHxUsBEcrXuy/p9xX+xmqC6Qah1m2yIg0JGVepK4BjlYaIpm B1TupwHbzyzUy9vciTMu/MU0AFCb6q73vxMjPQbGSLA5vM/ykqqzl4DAC6nUFJD93y2TU5IGW8+Rh j3gihTY/Q==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kctXG-0002xQ-P0; Wed, 11 Nov 2020 17:03:54 +0000 Received: from mail-pj1-x1044.google.com ([2607:f8b0:4864:20::1044]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kctXC-0002wK-Pc for linux-arm-kernel@lists.infradead.org; Wed, 11 Nov 2020 17:03:52 +0000 Received: by mail-pj1-x1044.google.com with SMTP id r9so998906pjl.5 for ; Wed, 11 Nov 2020 09:03:50 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=date:from:to:cc:subject:message-id:references:mime-version :content-disposition:in-reply-to; bh=VnerPPbUmuZFnp4YYpn03IqKxLwo6asabfmmClFT9fk=; b=WV+GTPvFQ7e3vbRuV5ZZANRijLqIYm0YiHShoPdzRxVt1Lmzk7j5RUVtHq+Wcy/B5h Uc/q0OUxmcoVWNMYBEXrzSvGznyzTH5HLSZsZqDT0NG22F97q2gkH5/W/lgnjvsHruYK kI74xkK0HhKAW57v750IM4SHmk2uZMjgKpwJKt0E7RfVQIZoG5lJQ0MlrrNUBkX3PpCr QFIE7mhirI3rMItUo+KrUg48K1QjuYBd+2zjVrGtSNNCXmZ2GVwmpXiJa0zOdp6D7jcI vdFWFei2dcaVg+B4TloKPhQ3zSp3dCJFHah0jVZTTstXWuBvFkMiYH5SCuudtnxm01Bs u88A== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:date:from:to:cc:subject:message-id:references :mime-version:content-disposition:in-reply-to; bh=VnerPPbUmuZFnp4YYpn03IqKxLwo6asabfmmClFT9fk=; b=sSW5A2gseBdPEzfpfvqZv74i5rj4B4Xg+ZLoSvBl+znpcADICThOlepgdX5YISoRUr IegTnoPlMyqCEOHWJr2moVXQp+WL5FS9FPkTvncayq5UscJzsYQBqVulrL9d8eAbUKqO Ry7ZpvTg88FwDgaNtI3IDOA6Inj8MWxk0yAIsUbTbFVATzdHSnXMwAHfZWNJACMrOTir eIne5lhNQP+HTP9PEKOxCm0Bna5ceC4yFEAL9UPPcAy/yp7KyhjRiGbJHhngs7bTJ/AM DwDXu+rHZ6kjyiJlkTRF2vdYiYm+9vcephjrJTdQS5mxrXaXUkrtHPMYDgwjPtAwUd1H xLyw== X-Gm-Message-State: AOAM533mZdTShhrspmbE/RTOXfwUEsiF02buGSX3XsYDrahmsx3OKIGG Fs777ulePKtq5sjK6XsYUCC6/w== X-Google-Smtp-Source: ABdhPJzMIueM3OdQv8L2EhKMPoPcWp2op5c3osuDjN0EKyHBe2PUm5Sv7oENl27mjVONM0KVpHjIMQ== X-Received: by 2002:a17:902:d90d:b029:d6:ecf9:c1dd with SMTP id c13-20020a170902d90db02900d6ecf9c1ddmr21742544plz.13.1605114228419; Wed, 11 Nov 2020 09:03:48 -0800 (PST) Received: from xps15 (S0106002369de4dac.cg.shawcable.net. [68.147.8.254]) by smtp.gmail.com with ESMTPSA id z16sm3317771pfq.179.2020.11.11.09.03.46 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 11 Nov 2020 09:03:47 -0800 (PST) Date: Wed, 11 Nov 2020 10:03:45 -0700 From: Mathieu Poirier To: Qi Liu Subject: Re: [RFC PATCH v2] coresight: etm4x: Modify core-commit of cpu to avoid the overflow of HiSilicon ETM Message-ID: <20201111170345.GA3543438@xps15> References: <1597824397-29894-1-git-send-email-liuqi115@huawei.com> <20200827204426.GD22307@xps15> <548c973d-6964-ca5c-4c8d-fbc2386f3349@arm.com> <20200909162605.GB553266@xps15> <70f83c48-5a4e-5d4d-734f-105501d21a63@huawei.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <70f83c48-5a4e-5d4d-734f-105501d21a63@huawei.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_120351_076362_C1D28C30 X-CRM114-Status: GOOD ( 46.75 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Suzuki K Poulose , Greg Kroah-Hartman , Coresight ML , linuxarm@huawei.com, Linux Kernel Mailing List , linux-arm-kernel , Mike Leach Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Nov 11, 2020 at 04:58:23PM +0800, Qi Liu wrote: > Hi Mathieu, > > On 2020/9/10 0:26, Mathieu Poirier wrote: > > On Wed, Sep 09, 2020 at 12:30:02PM +0100, Mike Leach wrote: > >> Hi, > >> > >> On Wed, 2 Sep 2020 at 11:36, Suzuki K Poulose wrote: > >>> On 08/27/2020 09:44 PM, Mathieu Poirier wrote: > >>>> Hi Liu, > >>>> > >>>> On Wed, Aug 19, 2020 at 04:06:37PM +0800, Qi Liu wrote: > >>>>> When too much trace information is generated on-chip, the ETM will > >>>>> overflow, and cause data loss. This is a common phenomenon on ETM > >>>>> devices. > >>>>> > >>>>> But sometimes we do not want to lose performance trace data, so we > >>>>> suppress the speed of instructions sent from CPU core to ETM to > >>>>> avoid the overflow of ETM. > >>>>> > >>>>> Signed-off-by: Qi Liu > >>>>> --- > >>>>> > >>>>> Changes since v1: > >>>>> - ETM on HiSilicon Hip09 platform supports backpressure, so does > >>>>> not need to modify core commit. > >>>>> > >>>>> drivers/hwtracing/coresight/coresight-etm4x.c | 43 +++++++++++++++++++++++++++ > >>>>> 1 file changed, 43 insertions(+) > >>>>> > >>>>> diff --git a/drivers/hwtracing/coresight/coresight-etm4x.c b/drivers/hwtracing/coresight/coresight-etm4x.c > >>>>> index 7797a57..7641f89 100644 > >>>>> --- a/drivers/hwtracing/coresight/coresight-etm4x.c > >>>>> +++ b/drivers/hwtracing/coresight/coresight-etm4x.c > >>>>> @@ -43,6 +43,10 @@ MODULE_PARM_DESC(boot_enable, "Enable tracing on boot"); > >>>>> #define PARAM_PM_SAVE_NEVER 1 /* never save any state */ > >>>>> #define PARAM_PM_SAVE_SELF_HOSTED 2 /* save self-hosted state only */ > >>>>> > >>>>> +#define CORE_COMMIT_CLEAR 0x3000 > >>>>> +#define CORE_COMMIT_SHIFT 12 > >>>>> +#define HISI_ETM_AMBA_ID_V1 0x000b6d01 > >>>>> + > >>>>> static int pm_save_enable = PARAM_PM_SAVE_FIRMWARE; > >>>>> module_param(pm_save_enable, int, 0444); > >>>>> MODULE_PARM_DESC(pm_save_enable, > >>>>> @@ -104,11 +108,40 @@ struct etm4_enable_arg { > >>>>> int rc; > >>>>> }; > >>>>> > >>>>> +static void etm4_cpu_actlr1_cfg(void *info) > >>>>> +{ > >>>>> + struct etm4_enable_arg *arg = (struct etm4_enable_arg *)info; > >>>>> + u64 val; > >>>>> + > >>>>> + asm volatile("mrs %0,s3_1_c15_c2_5" : "=r"(val)); > >>> > >>> The ID register (S3_1_C15_c2_5) falls into implementation defined space. > >>> See Arm ARM DDI 0487F.a, section "D12.3.2 Reserved encodings for > >>> IMPLEMENTATION DEFINED registers". > >>> > >>> So, please stop calling this "etm4_cpu_actlr1_cfg". Since, > >>> 1) actlr1 is not an architected name for the said encoding > >>> 2) The id register could mean something else on another CPU. > >>> > >>> Rather this should indicate platform/CPU specific. e.g, > >>> > >>> etm4_cpu_hisilicon_config_core_commit() > >>> > >>> > >>>>> + val &= ~CORE_COMMIT_CLEAR; > >>>>> + val |= arg->rc << CORE_COMMIT_SHIFT; > >>>>> + asm volatile("msr s3_1_c15_c2_5,%0" : : "r"(val)); > >>>>> +} > >>>>> + > >>>>> +static void etm4_config_core_commit(int cpu, int val) > >>>>> +{ > >>>>> + struct etm4_enable_arg arg = {0}; > >>>>> + > >>>>> + arg.rc = val; > >>>>> + smp_call_function_single(cpu, etm4_cpu_actlr1_cfg, &arg, 1); > >>>> Function etm4_enable/disable_hw() are already running on the CPU they are > >>>> supposed to so no need to call smp_call_function_single(). > >>>> > >>>>> +} > >>>>> + > >>>>> static int etm4_enable_hw(struct etmv4_drvdata *drvdata) > >>>>> { > >>>>> int i, rc; > >>>>> + struct amba_device *adev; > >>>>> struct etmv4_config *config = &drvdata->config; > >>>>> struct device *etm_dev = &drvdata->csdev->dev; > >>>>> + struct device *dev = drvdata->csdev->dev.parent; > >>>>> + > >>>>> + adev = container_of(dev, struct amba_device, dev); > >>>>> + /* > >>>>> + * If ETM device is HiSilicon ETM device, reduce the > >>>>> + * core-commit to avoid ETM overflow. > >>>>> + */ > >>>>> + if (adev->periphid == HISI_ETM_AMBA_ID_V1) > >>> Please could you move this check to the function above ? > >>> Ideally, it would be good to have something like : > >>> > >>> etm4_config_impdef_features(); > >>> > >>> And : > >>> > >>> etm4_config_impdef_features(struct etm4_drvdata *drvdata) > >>> { > >>> etm4_cpu_hisilicon_config_core_commit(drvdata); > >>> } > >>> > >> In addition to the above, Is it worth having this implementation > >> defined code gated in the kernel configuration - like we do for core > >> features sometimes? > >> i,.e. > >> CONFIG_ETM4X_IMPDEF_FEATURE (controls overall impdef support in the driver) > >> and > >> CONFIG_ETM4X_IMPDEF_HISILICON (depends on CONFIG_ETM4X_IMPDEF_FEATURE ) > >> > >> This way we keep non ETM architectural code off platforms that cannot > >> use it / test it. > >> > > That's a good idea - they do the same for CPU erratas. > > > Considering that users sometimes use the same set of code on different platforms, how about > using both CONFIG andperiphid to keep core-commit code off the platforms that do not > need it? > i, .e. > CONFIG_ETM4X_IMPDEF_FEATURE ( controls overall impdef support in the driver ) > periphid ( match impdef code with the target platform ) > > This way we could keep the same set of code working on different platforms, and it could help to > ensure compatibility. I'm not 100% sure of what you mean by "same set of code working on different platforms"... Up to know the way we have been handling peripheral IDs has worked quite well and I don't intend on changing it unless there is a really good reason. > I'll update this patch if this solution is ok : ) > > Thanks! > Qi > >>>> Do you have any documentation on this back pressure feature? I doubt this is > >>>> specific to Hip09 platform and as such would prefer to have a more generic > >>>> approach that works on any platform that supports it. > >>>> > >>>> Anyone on the CS mailing list that knows what this is about? > >>> I believe this is hisilicon specific. May be same across their CPUs, may > >>> be a specific one. There is no architectural guarantee. > >>> > >> This could be an implementation of the feature provided by the > >> TRCSTALLCTRL register - which allows PE to be stalled in response to > >> the ETM fifos approaching overflow. > >> At present we do nothing with this feature as we have yet to see a > >> target with it implemented, but if this is the case then it is an > >> ETMv4 architectural feature that could be added into the main driver > >> code, with use/access gated by the relevent TRCIDR bit. > >> > >> Regards > >> > >> Mike > >> > >> > >>> Cheers > >>> Suzuki > >> > >> > >> -- > >> Mike Leach > >> Principal Engineer, ARM Ltd. > >> Manchester Design Centre. UK > > . > > > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel