From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 9D696C388F9 for ; Wed, 11 Nov 2020 19:12:01 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 03DBF206F1 for ; Wed, 11 Nov 2020 19:12:00 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="bjyXqMK+" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 03DBF206F1 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GE4mHvrgA04B6c52d2XtvxQD+w7MVEhyq+hVGMOCSGo=; b=bjyXqMK+oXepnDw8e7ggiODar TXQOOUFrSQpsl6sBkYaziU64gPDvuX0e9ho/dIdJCNSbefsTFnCRpoMScr95tr45gfobvae6erfWX oqrWGELvAPzwlleS0P81N/VwQcnqfeReaLAQgZpMRrrsnjnjnObHAMgGU/C0BUSMAuobom5s8uLiE 7mmwavukd0Qvu+diRnYlI5dZkCHVSWgJBXq5J8nPLKwPHfjofjshXo5zLv0LMO0wPW+qI3oZW1PWk DqvzQFMGn0MrcKV1c5qVDibQeh6qA3XEF2XNj6khyV3wJPobNmH6qKtqE7nVXP8cJEpgrRzzNiai9 HT+3Gt4YQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcvWA-00056o-5C; Wed, 11 Nov 2020 19:10:54 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kcvW6-00054y-Bx for linux-arm-kernel@lists.infradead.org; Wed, 11 Nov 2020 19:10:51 +0000 Received: from gaia (unknown [2.26.170.190]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id E88FB206FB; Wed, 11 Nov 2020 19:10:46 +0000 (UTC) Date: Wed, 11 Nov 2020 19:10:44 +0000 From: Catalin Marinas To: Will Deacon Subject: Re: [PATCH v2 2/6] arm64: Allow mismatched 32-bit EL0 support Message-ID: <20201111191043.GA5125@gaia> References: <20201109213023.15092-1-will@kernel.org> <20201109213023.15092-3-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201109213023.15092-3-will@kernel.org> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201111_141050_638720_68EC66FE X-CRM114-Status: GOOD ( 19.48 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, kernel-team@android.com, Quentin Perret , Peter Zijlstra , Marc Zyngier , Qais Yousef , Greg Kroah-Hartman , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Will, On Mon, Nov 09, 2020 at 09:30:18PM +0000, Will Deacon wrote: > +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > +{ > + if (!has_cpuid_feature(entry, scope)) > + return allow_mismatched_32bit_el0; I still don't like overriding the cpufeature mechanism in this way. What about something like below? It still doesn't fit perfectly but at least the capability represents what was detected in the system. We then decide in system_supports_32bit_el0() whether to allow asymmetry. There is an extra trick to park a non-AArch32 capable CPU in has_32bit_el0() if it comes up late and the feature has already been advertised with !allow_mismatched_32bit_el0. I find it clearer, though I probably stared at it more than at your patch ;). diff --git a/arch/arm64/include/asm/cpufeature.h b/arch/arm64/include/asm/cpufeature.h index 97244d4feca9..0e0427997063 100644 --- a/arch/arm64/include/asm/cpufeature.h +++ b/arch/arm64/include/asm/cpufeature.h @@ -604,9 +604,13 @@ static inline bool cpu_supports_mixed_endian_el0(void) return id_aa64mmfr0_mixed_endian_el0(read_cpuid(ID_AA64MMFR0_EL1)); } +extern bool allow_mismatched_32bit_el0; +extern bool mismatched_32bit_el0; + static inline bool system_supports_32bit_el0(void) { - return cpus_have_const_cap(ARM64_HAS_32BIT_EL0); + return cpus_have_const_cap(ARM64_HAS_32BIT_EL0) && + (!mismatched_32bit_el0 || allow_mismatched_32bit_el0); } static inline bool system_supports_4kb_granule(void) diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c index b7b6804cb931..67534327f92b 100644 --- a/arch/arm64/kernel/cpufeature.c +++ b/arch/arm64/kernel/cpufeature.c @@ -104,6 +104,13 @@ DECLARE_BITMAP(boot_capabilities, ARM64_NPATCHABLE); bool arm64_use_ng_mappings = false; EXPORT_SYMBOL(arm64_use_ng_mappings); +/* + * Permit PER_LINUX32 and execve() of 32-bit binaries even if not all CPUs + * support it? + */ +bool __read_mostly allow_mismatched_32bit_el0; +bool mismatched_32bit_el0; + /* * Flag to indicate if we have computed the system wide * capabilities based on the boot time active CPUs. This @@ -1193,6 +1200,35 @@ has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) return feature_matches(val, entry); } +static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) +{ + if (has_cpuid_feature(entry, scope)) + return true; + + if (system_capabilities_finalized() && !allow_mismatched_32bit_el0) { + pr_crit("CPU%d: Asymmetric AArch32 not supported\n", + smp_processor_id()); + cpu_die_early(); + } + + mismatched_32bit_el0 = true; + return false; +} + +static int __init report_32bit_el0(void) +{ + if (!system_supports_32bit_el0()) + return 0; + + if (mismatched_32bit_el0) + pr_info("detected: asymmetric 32-bit EL0 support\n"); + else + pr_info("detected: 32-bit EL0 support\n"); + + return 0; +} +core_initcall(report_32bit_el0); + static bool has_useable_gicv3_cpuif(const struct arm64_cpu_capabilities *entry, int scope) { bool has_sre; @@ -1800,10 +1836,9 @@ static const struct arm64_cpu_capabilities arm64_features[] = { }, #endif /* CONFIG_ARM64_VHE */ { - .desc = "32-bit EL0 Support", .capability = ARM64_HAS_32BIT_EL0, - .type = ARM64_CPUCAP_SYSTEM_FEATURE, - .matches = has_cpuid_feature, + .type = ARM64_CPUCAP_WEAK_LOCAL_CPU_FEATURE, + .matches = has_32bit_el0, .sys_reg = SYS_ID_AA64PFR0_EL1, .sign = FTR_UNSIGNED, .field_pos = ID_AA64PFR0_EL0_SHIFT, -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel