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Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by casper.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kee55-0004fe-Ri; Mon, 16 Nov 2020 12:58:04 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 79A623060AE; Mon, 16 Nov 2020 13:58:03 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 65CAB202647A8; Mon, 16 Nov 2020 13:58:03 +0100 (CET) Date: Mon, 16 Nov 2020 13:58:03 +0100 From: Peter Zijlstra To: Mel Gorman Subject: Re: Loadavg accounting error on arm64 Message-ID: <20201116125803.GB3121429@hirez.programming.kicks-ass.net> References: <20201116091054.GL3371@techsingularity.net> <20201116114938.GN3371@techsingularity.net> <20201116125355.GB3121392@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201116125355.GB3121392@hirez.programming.kicks-ass.net> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Davidlohr Bueso , Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 16, 2020 at 01:53:55PM +0100, Peter Zijlstra wrote: > On Mon, Nov 16, 2020 at 11:49:38AM +0000, Mel Gorman wrote: > > On Mon, Nov 16, 2020 at 09:10:54AM +0000, Mel Gorman wrote: > > > I'll be looking again today to see can I find a mistake in the ordering for > > > how sched_contributes_to_load is handled but again, the lack of knowledge > > > on the arm64 memory model means I'm a bit stuck and a second set of eyes > > > would be nice :( > > > > > > > This morning, it's not particularly clear what orders the visibility of > > sched_contributes_to_load exactly like other task fields in the schedule > > vs try_to_wake_up paths. I thought the rq lock would have ordered them but > > something is clearly off or loadavg would not be getting screwed. It could > > be done with an rmb and wmb (testing and hasn't blown up so far) but that's > > far too heavy. smp_load_acquire/smp_store_release might be sufficient > > on it although less clear if the arm64 gives the necessary guarantees. > > > > (This is still at the chucking out ideas as I haven't context switched > > back in all the memory barrier rules). > > IIRC it should be so ordered by ->on_cpu. > > We have: > > schedule() > prev->sched_contributes_to_load = X; > smp_store_release(prev->on_cpu, 0); > > > on the one hand, and: Ah, my bad, ttwu() itself will of course wait for !p->on_cpu before we even get here. > sched_ttwu_pending() > if (WARN_ON_ONCE(p->on_cpu)) > smp_cond_load_acquire(&p->on_cpu) > > ttwu_do_activate() > if (p->sched_contributes_to_load) > ... > > on the other (for the remote case, which is the only 'interesting' one). Also see the "Notes on Program-Order guarantees on SMP systems." comment. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel