From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-6.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A01CBC4742C for ; Mon, 16 Nov 2020 16:50:03 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 19D0620776 for ; Mon, 16 Nov 2020 16:50:03 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Dtbi90oa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 19D0620776 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=infradead.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=cy0VX4ZQbBlVSZj5/BVuRgOAIZi4iNWM7CISDkhOJ8A=; b=Dtbi90oaijMQKCT+q4lOsgQQm dX0J+22pDAyInDJKIRJftFuurt0JgMRucs0eo1/HkIFqEb5v/WH1PKHouSKzvBEZvrLxUdNgUJ2h5 bIB5mhST17O6gD1qpWmyS4UPL7BH0Op4vCH209TmSXJz+PGszRVrdG0xQpUX9qRWs4flrQTw11gdg KhYtdyXY8Ba0ANIbc/TZXhHwfv1l7EiXXZgQL8noCWHsPxd/wAdeDuHNIQ0dQ771lQNdv16YadyHA +y1/sf2Pk5st8mYj0P16pVe389ZsMO1sEHMs1PesJdZJgK9N0IN5wbCLMVPNeee2TL4cSHx92RfWb 0GoYjDxcA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kehh6-0002I7-MV; Mon, 16 Nov 2020 16:49:32 +0000 Received: from j217100.upc-j.chello.nl ([24.132.217.100] helo=noisy.programming.kicks-ass.net) by merlin.infradead.org with esmtpsa (Exim 4.92.3 #3 (Red Hat Linux)) id 1kehh4-0002Hc-H6; Mon, 16 Nov 2020 16:49:30 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 27A493012C3; Mon, 16 Nov 2020 17:49:28 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 1BA9A20282DFC; Mon, 16 Nov 2020 17:49:28 +0100 (CET) Date: Mon, 16 Nov 2020 17:49:28 +0100 From: Peter Zijlstra To: Mel Gorman Subject: Re: Loadavg accounting error on arm64 Message-ID: <20201116164928.GF3121392@hirez.programming.kicks-ass.net> References: <20201116091054.GL3371@techsingularity.net> <20201116114938.GN3371@techsingularity.net> <20201116125355.GB3121392@hirez.programming.kicks-ass.net> <20201116125803.GB3121429@hirez.programming.kicks-ass.net> <20201116152946.GR3371@techsingularity.net> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201116152946.GR3371@techsingularity.net> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Davidlohr Bueso , Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 16, 2020 at 03:29:46PM +0000, Mel Gorman wrote: > On Mon, Nov 16, 2020 at 01:58:03PM +0100, Peter Zijlstra wrote: > > > sched_ttwu_pending() > > > if (WARN_ON_ONCE(p->on_cpu)) > > > smp_cond_load_acquire(&p->on_cpu) > > > > > > ttwu_do_activate() > > > if (p->sched_contributes_to_load) > > > ... > > > > > > on the other (for the remote case, which is the only 'interesting' one). > > > > But this side is interesting because I'm having trouble convincing > myself it's 100% correct for sched_contributes_to_load. The write of > prev->sched_contributes_to_load in the schedule() path has a big gap > before it hits the smp_store_release(prev->on_cpu). > > On the ttwu path, we have > > if (smp_load_acquire(&p->on_cpu) && > ttwu_queue_wakelist(p, task_cpu(p), wake_flags | WF_ON_CPU)) > goto unlock; > > ttwu_queue_wakelist queues task on the wakelist, sends IPI > and on the receiver side it calls ttwu_do_activate and reads > sched_contributes_to_load > > sched_ttwu_pending() is not necessarily using the same rq lock so no > protection there. The smp_load_acquire() has just been hit but it still > leaves a gap between when sched_contributes_to_load is written and a > parallel read of sched_contributes_to_load. > > So while we might be able to avoid a smp_rmb() before the read of > sched_contributes_to_load and rely on p->on_cpu ordering there, > we may still need a smp_wmb() after nr_interruptible() increments > instead of waiting until the smp_store_release() is hit while a task > is scheduling. That would be a real memory barrier on arm64 and a plain > compiler barrier on x86-64. I'm mighty confused by your words here; and the patch below. What actual scenario are you worried about? If we take the WF_ON_CPU path, we IPI the CPU the task is ->on_cpu on. So the IPI lands after the schedule() that clears ->on_cpu on the very same CPU. > > > Also see the "Notes on Program-Order guarantees on SMP systems." > > comment. > > I did, it was the on_cpu ordering for the blocking case that had me > looking at the smp_store_release and smp_cond_load_acquire in arm64 in > the first place thinking that something in there must be breaking the > on_cpu ordering. I'm re-reading it every so often while trying to figure > out where the gap is or whether I'm imagining things. > > Not fully tested but did not instantly break either > > diff --git a/kernel/sched/core.c b/kernel/sched/core.c > index d2003a7d5ab5..877eaeba45ac 100644 > --- a/kernel/sched/core.c > +++ b/kernel/sched/core.c > @@ -4459,14 +4459,26 @@ static void __sched notrace __schedule(bool preempt) > if (signal_pending_state(prev_state, prev)) { > prev->state = TASK_RUNNING; > } else { > - prev->sched_contributes_to_load = > + int acct_load = > (prev_state & TASK_UNINTERRUPTIBLE) && > !(prev_state & TASK_NOLOAD) && > !(prev->flags & PF_FROZEN); > > - if (prev->sched_contributes_to_load) > + prev->sched_contributes_to_load = acct_load; > + if (acct_load) { > rq->nr_uninterruptible++; > > + /* > + * Pairs with p->on_cpu ordering, either a > + * smp_load_acquire or smp_cond_load_acquire > + * in the ttwu path before ttwu_do_activate > + * p->sched_contributes_to_load. It's only > + * after the nr_interruptible update happens > + * that the ordering is critical. > + */ > + smp_wmb(); > + } Sorry, I can't follow, at all. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel