From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.8 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A0C58C56202 for ; Fri, 20 Nov 2020 10:14:55 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 1BB42222BA for ; Fri, 20 Nov 2020 10:14:55 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="c2S3oeIK" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 1BB42222BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Q0jyTJ9+Q4/SJOdl/xqlqHU0s2RsA8ZmE8sDJ51QzSQ=; b=c2S3oeIKWtadGjf7Xn87o7Brz RXFD7uG/9CD6R+f/7bhWMdALWljvl3I9JQOOMt4u4fwhbxKxNb2BFa73Fgr+2FAaHjpRizkzyJqRt 23OdXKHRpZE5DZVsL0Zzpqwfvb8eBrxVyaq13E06lhUU2qrsAB962Tz7PUZBac2Y7vteKKD8hveWh Vo8p+MYJpji1JP52kVD6ZNL2XHOe4AqGoqJGpX7HuOnM8fjWHr+xqt3/S1hyvWOMkPxeGygoH/SY9 5/m51Gnl92ZRwq0ZhnAvQGhLUZf1+TB/WA4w4nWQ8qp5ut4dD++5VJhTBgA9ntbCsqzsp+cPl3ASN +z0mxqM2g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kg3QB-0006No-Pe; Fri, 20 Nov 2020 10:13:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kg3Q7-0006Mc-OA for linux-arm-kernel@lists.infradead.org; Fri, 20 Nov 2020 10:13:36 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 3975B1042; Fri, 20 Nov 2020 02:13:34 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.27.176]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 93C723F70D; Fri, 20 Nov 2020 02:13:31 -0800 (PST) Date: Fri, 20 Nov 2020 10:13:24 +0000 From: Mark Rutland To: Vladimir Murzin Subject: Re: AMU extension v1 support for cortex A76, A77, A78 CPUs Message-ID: <20201120101249.GA2328@C02TD0UTHF1T.local> References: <2cc9dd44-0b4b-94a8-155a-7a2446a1b892@codeaurora.org> <1712842eb0767e51155a5396d282102c@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201120_051335_929777_FF056832 X-CRM114-Status: GOOD ( 20.01 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, Will Deacon , suzuki.poulose@arm.com, Marc Zyngier , lkml , valentin.schneider@arm.com, MSM , ionela.voinescu@arm.com, Neeraj Upadhyay , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 20, 2020 at 09:09:00AM +0000, Vladimir Murzin wrote: > On 11/20/20 8:56 AM, Marc Zyngier wrote: > > On 2020-11-20 04:30, Neeraj Upadhyay wrote: > >> Hi, > >> > >> For ARM cortex A76, A77, A78 cores (which as per TRM, support AMU) > >> AA64PFR0[47:44] field is not set, and AMU does not get enabled for > >> them. > >> Can you please provide support for these CPUs in cpufeature.c? > > > > If that was the case, that'd be an erratum, and it would need to be > > documented as such. It could also be that this is an optional feature > > for these cores (though the TRM doesn't suggest that). > > > > Can someone at ARM confirm what is the expected behaviour of these CPUs? > > Not a confirmation, but IIRC, these are imp def features, while our cpufeatures > catches architected one. We generally don't make use of IMP-DEF featurees because of all the pain it brings. Looking at the Cortex-A76 TRM, the encoding for AMCNTENCLR is: Op0: 3 (0b11) Op1: 3 (0b011) CRn: 15 (0b1111) CRm: 9 (0b1001) Op2: 7 (0b111) ... whereas the architected encoding (from our sysreg.h) is: Op0: 3 Op1: 3 CRn: 13 CRm: 2 Op2: 4 ... so that's a different register with the same name, which is confusing and unfortunate. The encodings are different (and I haven't checked whether the fields / semantics are the same), so it's not just a matter of wiring up new detection code. There are also IMP-DEF traps in ACTLR_EL3 and ACTLR_EL2 which we can't be certain of the configuration of, and as the registers are in the IMP-DEF encoding space they'll be trapped by HCR_EL2.TIDCP and emulated as UNDEFINED by a hypervisor. All of that means that going by the MIDR alone is not sufficient to know we can safely access the registers. So as usual for IMP-DEF stuff I don't think we can or should make use of this. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel