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[24.155.109.49]) by smtp.gmail.com with ESMTPSA id j8sm2384607oif.55.2020.11.20.14.08.20 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 Nov 2020 14:08:21 -0800 (PST) Received: (nullmailer pid 1840593 invoked by uid 1000); Fri, 20 Nov 2020 22:08:20 -0000 Date: Fri, 20 Nov 2020 16:08:20 -0600 From: Rob Herring To: Will Deacon , Mark Rutland Subject: Re: [PATCH v4 2/9] arm64: perf: Enable pmu counter direct access for perf event on armv8 Message-ID: <20201120220820.GA1802040@robh.at.kernel.org> References: <20201001140116.651970-1-robh@kernel.org> <20201001140116.651970-3-robh@kernel.org> <20201113180633.GE44988@C02TD0UTHF1T.local> <20201119191515.GA4906@willie-the-truck> <20201120200345.GA1194400@robh.at.kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201120200345.GA1194400@robh.at.kernel.org> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201120_170823_531649_1821868C X-CRM114-Status: GOOD ( 26.32 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Ian Rogers , Peter Zijlstra , Catalin Marinas , linux-kernel@vger.kernel.org, Arnaldo Carvalho de Melo , Alexander Shishkin , Raphael Gault , Ingo Molnar , honnappa.nagarahalli@arm.com, Jonathan Cameron , Namhyung Kim , Itaru Kitayama , Jiri Olsa , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 20, 2020 at 02:03:45PM -0600, Rob Herring wrote: > On Thu, Nov 19, 2020 at 07:15:15PM +0000, Will Deacon wrote: > > On Fri, Nov 13, 2020 at 06:06:33PM +0000, Mark Rutland wrote: > > > On Thu, Oct 01, 2020 at 09:01:09AM -0500, Rob Herring wrote: > > > > +static void armv8pmu_event_unmapped(struct perf_event *event, struct mm_struct *mm) > > > > +{ > > > > + if (!(event->hw.flags & ARMPMU_EL0_RD_CNTR)) > > > > + return; > > > > + > > > > + if (atomic_dec_and_test(&mm->context.pmu_direct_access)) > > > > + on_each_cpu_mask(mm_cpumask(mm), refresh_pmuserenr, NULL, 1); > > > > +} > > > > > > I didn't think we kept our mm_cpumask() up-to-date in all cases on > > > arm64, so I'm not sure we can use it like this. > > > > > > Will, can you confirm either way? > > > > We don't update mm_cpumask() as the cost of the atomic showed up in some > > benchmarks I did years ago and we've never had any need for the thing anyway > > because out TLB invalidation is one or all. > > That's good because we're also passing NULL instead of mm which would > crash. So it must be more than it's not up to date, but it's always 0. > It looks like event_mapped on x86 uses mm_cpumask(mm) which I guess was > dropped when copying this code as it didn't work... For reference, the > x86 version of this originated in commit 7911d3f7af14a6. > > I'm not clear on why we need to update pmuserenr_el0 here anyways. To > get here userspace has to mmap the event and then unmmap it. If we did > nothing, then counter accesses would not fault until the next context > switch. > > If you all have any ideas, I'm all ears. I'm not a scheduler nor perf > hacker. ;) Here's another issue that needs addressing: https://lore.kernel.org/lkml/20200821195754.20159-3-kan.liang@linux.intel.com/ Rob _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel