From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4B66EC2D0E4 for ; Mon, 23 Nov 2020 14:32:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id D913A20781 for ; Mon, 23 Nov 2020 14:32:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="rm7MW0Vm" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org D913A20781 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=Kh+xjq+i7gceRnb2erUc/ZM5TvWYdyuMel7eNQih6/0=; b=rm7MW0Vm6Z2rHa8tnlBfgJARj eVzwoQ8Apmvl3oUV049ZFyh0Y4387BV681a+q10XS3oBHS8eAhPoQDXIWKzBzhT/M0WmZpYccyvD/ q1/Yh6lrQ1bX9iXdK2s5EUhJGNvNNhBND6dWqTk3vbSmWvWgJ14/+AcWrVQj7gOfY4DYTtC88CD4N k5CfynBMmPNZkrNGuJaUBmMdm1uFnSTw+fHJuE9321ZT8ABMAFKiNp3YSOpr7Le6xgIYuN0L2gyJr Tw/YXYwBiC1D4F841VEycuHS+BRRK2DkedcHYlHQAwJWy6gaWS/wOUf8wqw+WGtV0602g+PL6Z1gP FsOnzAaZA==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1khCsn-0007DU-D7; Mon, 23 Nov 2020 14:31:57 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1khCsl-0007CO-4N for linux-arm-kernel@lists.infradead.org; Mon, 23 Nov 2020 14:31:56 +0000 Received: from gaia (unknown [95.146.230.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 74C3820781; Mon, 23 Nov 2020 14:31:52 +0000 (UTC) Date: Mon, 23 Nov 2020 14:31:49 +0000 From: Catalin Marinas To: Minchan Kim Subject: Re: [PATCH 2/6] arm64: pgtable: Ensure dirty bit is preserved across pte_wrprotect() Message-ID: <20201123143149.GG17833@gaia> References: <20201120143557.6715-1-will@kernel.org> <20201120143557.6715-3-will@kernel.org> <20201120170903.GC3377168@google.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201120170903.GC3377168@google.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201123_093155_382203_B6721BA1 X-CRM114-Status: GOOD ( 18.89 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Yu Zhao , Anshuman Khandual , Peter Zijlstra , Will Deacon , Linus Torvalds , linux-kernel@vger.kernel.org, stable@vger.kernel.org, linux-mm@kvack.org, kernel-team@android.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 20, 2020 at 09:09:03AM -0800, Minchan Kim wrote: > On Fri, Nov 20, 2020 at 02:35:53PM +0000, Will Deacon wrote: > > With hardware dirty bit management, calling pte_wrprotect() on a writable, > > dirty PTE will lose the dirty state and return a read-only, clean entry. > > > > Move the logic from ptep_set_wrprotect() into pte_wrprotect() to ensure that > > the dirty bit is preserved for writable entries, as this is required for > > soft-dirty bit management if we enable it in the future. > > > > Cc: > > It this stable material if it would be a problem once ARM64 supports > softdirty in future? I don't think so. Arm64 did not have a hardware dirty mechanism from the start, it was added later but in a way as to coexist with other CPUs or peripherals that don't support it. So instead of setting a PTE_DIRTY bit as one would expect, the CPU clears the PTE_RDONLY on write access to a writable PTE (the PTE_DBM/PTE_WRITE bit set). So our pte_wrprotect() needs to set PTE_RDONLY and clear PTE_DBM (PTE_WRITE) but !PTE_RDONLY is our only information of a pte having been dirtied, so we have to transfer it to a software PTE_DIRTY bit. This is different from a soft-dirty pte bit if we add it in the future. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel