From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.3 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 42231C56202 for ; Wed, 25 Nov 2020 10:25:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C2D69206D9 for ; Wed, 25 Nov 2020 10:25:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="R5S2NeWa" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C2D69206D9 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=KQFe4FuJ1D2++73uNaklGB/oSj1OYej7loOsQaIskWg=; b=R5S2NeWaBTfY3X21hBUjrOxaw HNstxkYhf+MCZgT8AbJLXV5VV+vK2EX//IT8JEbD54DLz3OunfRilvpW5dnY9cdZhv7bjTRlDZglR wRsTMvL4S+zgP6Jekn9bX2r/STZ7CIctJeFnxw9kAGN5yzIdZl7WWfYQ6iVH1J7hS3TbAAhH4CoRR YB/MB8jAieG/+6u7YVxP8bWss372s5Lx+JE5pwQ0d0K/VHGr/SZUEBMQX2hj4HoGTr7wdk+gY2MCh 6u5Pt/cXjQKeD+PsYZX3aOxI4dD2wPYeElpLRb0o3TyAi0jaThsBiZ0GG1vOu51Mc0lYf/ZVVSkd+ Z7I/aCCyg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1khrxk-0007jC-Nd; Wed, 25 Nov 2020 10:23:48 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1khrxh-0007ia-KQ for linux-arm-kernel@lists.infradead.org; Wed, 25 Nov 2020 10:23:46 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id F25C2106F; Wed, 25 Nov 2020 02:23:35 -0800 (PST) Received: from e121166-lin.cambridge.arm.com (e121166-lin.cambridge.arm.com [10.1.196.255]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 6B4FC3F70D; Wed, 25 Nov 2020 02:23:34 -0800 (PST) Date: Wed, 25 Nov 2020 10:23:28 +0000 From: Lorenzo Pieralisi To: Bjorn Helgaas Subject: Re: [PATCH v8 3/3] PCI: uniphier: Add misc interrupt handler to invoke PME and AER Message-ID: <20201125102328.GA31700@e121166-lin.cambridge.arm.com> References: <1603848703-21099-4-git-send-email-hayashi.kunihiko@socionext.com> <20201124232037.GA595463@bjorn-Precision-5520> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201124232037.GA595463@bjorn-Precision-5520> User-Agent: Mutt/1.9.4 (2018-02-28) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201125_052345_781937_2511BBE6 X-CRM114-Status: GOOD ( 46.42 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Kunihiko Hayashi , Jingoo Han , Gustavo Pimentel , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Jassi Brar , Marc Zyngier , Bjorn Helgaas , Masami Hiramatsu , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Nov 24, 2020 at 05:20:37PM -0600, Bjorn Helgaas wrote: > On Wed, Oct 28, 2020 at 10:31:43AM +0900, Kunihiko Hayashi wrote: > > This patch adds misc interrupt handler to detect and invoke PME/AER event. > > > > In UniPhier PCIe controller, PME/AER signals are assigned to the same > > signal as MSI by the internal logic. These signals should be detected by > > the internal register, however, DWC MSI handler can't handle these signals. > > I don't know what "PME/AER signals are assigned to the same signal as > MSI" means. The host controller embeds an interrupt-controller whose IRQ wire output is cascaded into the main interrupt controller. The host-bridge embedded controller receives MSI writes from devices and it turns them into an edge IRQ into the main interrupt controller. To ack/mask the MSIs at host contoller interrupt controller level, there is a control register in the host controller that needs handling upon IRQ reception. The *RP* (and AFAIU the RP *only*) signals the PME/AER MSI using the same wire to the main interrupt controller but its ack/mask is handled by a different bit in the host bridge control register above, therefore the cascaded IRQ isr needs to know which virq it is actually handling to ack/mask accordingly. IMO this should be modelled with a separate IRQ domain and chip for the root port (yes this implies describing the root port in the dts file with a separate msi-parent). This series as it stands is a kludge. Lorenzo > I'm trying to figure out if this is talking about PME/AER MSI vector > numbers (probably not) or some internal wire that's not > architecturally visible or what. > > Probably also not related to the fact that PME, hotplug, and bandwidth > notifications share the same MSI/MSI-X vector. > > Is this something that's going to be applicable to all the DWC-based > drivers? > > > DWC MSI handler calls .msi_host_isr() callback function, that detects > > PME/AER signals with the internal register and invokes the interrupt > > with PME/AER vIRQ numbers. > > > > These vIRQ numbers is obtained from portdrv in uniphier_add_pcie_port() > > function. > > > > Cc: Marc Zyngier > > Cc: Jingoo Han > > Cc: Gustavo Pimentel > > Cc: Lorenzo Pieralisi > > Signed-off-by: Kunihiko Hayashi > > Reviewed-by: Rob Herring > > --- > > drivers/pci/controller/dwc/pcie-uniphier.c | 77 +++++++++++++++++++++++++----- > > 1 file changed, 66 insertions(+), 11 deletions(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-uniphier.c b/drivers/pci/controller/dwc/pcie-uniphier.c > > index 4817626..237537a 100644 > > --- a/drivers/pci/controller/dwc/pcie-uniphier.c > > +++ b/drivers/pci/controller/dwc/pcie-uniphier.c > > @@ -21,6 +21,7 @@ > > #include > > > > #include "pcie-designware.h" > > +#include "../../pcie/portdrv.h" > > > > #define PCL_PINCTRL0 0x002c > > #define PCL_PERST_PLDN_REGEN BIT(12) > > @@ -44,7 +45,9 @@ > > #define PCL_SYS_AUX_PWR_DET BIT(8) > > > > #define PCL_RCV_INT 0x8108 > > +#define PCL_RCV_INT_ALL_INT_MASK GENMASK(28, 25) > > #define PCL_RCV_INT_ALL_ENABLE GENMASK(20, 17) > > +#define PCL_RCV_INT_ALL_MSI_MASK GENMASK(12, 9) > > #define PCL_CFG_BW_MGT_STATUS BIT(4) > > #define PCL_CFG_LINK_AUTO_BW_STATUS BIT(3) > > #define PCL_CFG_AER_RC_ERR_MSI_STATUS BIT(2) > > @@ -68,6 +71,8 @@ struct uniphier_pcie_priv { > > struct reset_control *rst; > > struct phy *phy; > > struct irq_domain *legacy_irq_domain; > > + int aer_irq; > > + int pme_irq; > > }; > > > > #define to_uniphier_pcie(x) dev_get_drvdata((x)->dev) > > @@ -167,7 +172,15 @@ static void uniphier_pcie_stop_link(struct dw_pcie *pci) > > > > static void uniphier_pcie_irq_enable(struct uniphier_pcie_priv *priv) > > { > > - writel(PCL_RCV_INT_ALL_ENABLE, priv->base + PCL_RCV_INT); > > + u32 val; > > + > > + val = PCL_RCV_INT_ALL_ENABLE; > > + if (pci_msi_enabled()) > > + val |= PCL_RCV_INT_ALL_INT_MASK; > > + else > > + val |= PCL_RCV_INT_ALL_MSI_MASK; > > I'm confused about how this works. Root Ports can signal AER errors > with either INTx or MSI. This is controlled by the architected > Interrupt Disable bit and the MSI/MSI-X enable bits (I'm looking at > PCIe r5.0, sec 6.2.4.1.2). > > The code here doesn't look related to those bits. Does this code mean > that if pci_msi_enabled(), the Root Port will always signal with MSI > (if MSI Enable is set) and will *never* signal with INTx? > > > + writel(val, priv->base + PCL_RCV_INT); > > writel(PCL_RCV_INTX_ALL_ENABLE, priv->base + PCL_RCV_INTX); > > } > > > > @@ -231,28 +244,52 @@ static const struct irq_domain_ops uniphier_intx_domain_ops = { > > .map = uniphier_pcie_intx_map, > > }; > > > > -static void uniphier_pcie_irq_handler(struct irq_desc *desc) > > +static void uniphier_pcie_misc_isr(struct pcie_port *pp, bool is_msi) > > { > > - struct pcie_port *pp = irq_desc_get_handler_data(desc); > > struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); > > - struct irq_chip *chip = irq_desc_get_chip(desc); > > - unsigned long reg; > > - u32 val, bit, virq; > > + u32 val; > > > > - /* INT for debug */ > > val = readl(priv->base + PCL_RCV_INT); > > > > if (val & PCL_CFG_BW_MGT_STATUS) > > dev_dbg(pci->dev, "Link Bandwidth Management Event\n"); > > + > > Looks like a spurious whitespace change? > > > if (val & PCL_CFG_LINK_AUTO_BW_STATUS) > > dev_dbg(pci->dev, "Link Autonomous Bandwidth Event\n"); > > - if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) > > - dev_dbg(pci->dev, "Root Error\n"); > > - if (val & PCL_CFG_PME_MSI_STATUS) > > - dev_dbg(pci->dev, "PME Interrupt\n"); > > + > > + if (is_msi) { > > + if (val & PCL_CFG_AER_RC_ERR_MSI_STATUS) { > > + dev_dbg(pci->dev, "Root Error Status\n"); > > + if (priv->aer_irq) > > + generic_handle_irq(priv->aer_irq); > > + } > > + > > + if (val & PCL_CFG_PME_MSI_STATUS) { > > + dev_dbg(pci->dev, "PME Interrupt\n"); > > + if (priv->pme_irq) > > + generic_handle_irq(priv->pme_irq); > > + } > > + } > > > > writel(val, priv->base + PCL_RCV_INT); > > +} > > + > > +static void uniphier_pcie_msi_host_isr(struct pcie_port *pp) > > +{ > > + uniphier_pcie_misc_isr(pp, true); > > +} > > + > > +static void uniphier_pcie_irq_handler(struct irq_desc *desc) > > +{ > > + struct pcie_port *pp = irq_desc_get_handler_data(desc); > > + struct dw_pcie *pci = to_dw_pcie_from_pp(pp); > > + struct uniphier_pcie_priv *priv = to_uniphier_pcie(pci); > > + struct irq_chip *chip = irq_desc_get_chip(desc); > > + unsigned long reg; > > + u32 val, bit, virq; > > + > > + uniphier_pcie_misc_isr(pp, false); > > > > /* INTx */ > > chained_irq_enter(chip, desc); > > @@ -329,6 +366,7 @@ static int uniphier_pcie_host_init(struct pcie_port *pp) > > > > static const struct dw_pcie_host_ops uniphier_pcie_host_ops = { > > .host_init = uniphier_pcie_host_init, > > + .msi_host_isr = uniphier_pcie_msi_host_isr, > > }; > > > > static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, > > @@ -337,6 +375,7 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, > > struct dw_pcie *pci = &priv->pci; > > struct pcie_port *pp = &pci->pp; > > struct device *dev = &pdev->dev; > > + struct pci_dev *pcidev; > > int ret; > > > > pp->ops = &uniphier_pcie_host_ops; > > @@ -353,6 +392,22 @@ static int uniphier_add_pcie_port(struct uniphier_pcie_priv *priv, > > return ret; > > } > > > > + /* irq for PME */ > > + list_for_each_entry(pcidev, &pp->bridge->bus->devices, bus_list) { > > + priv->pme_irq = > > + pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_PME); > > + if (priv->pme_irq) > > + break; > > Does this mean that all Root Ports must use the same MSI vector? I > don't think that's a PCIe spec requirement, though of course DWC may > have its own restrictions. > > I don't think this depends on CONFIG_PCIEPORTBUS, so it looks like > it's possible to have > > # CONFIG_PCIEPORTBUS is not set > PCIE_UNIPHIER=y > > in which case I think you'll have a link error. > > > + } > > + > > + /* irq for AER */ > > + list_for_each_entry(pcidev, &pp->bridge->bus->devices, bus_list) { > > + priv->aer_irq = > > + pcie_port_service_get_irq(pcidev, PCIE_PORT_SERVICE_AER); > > + if (priv->aer_irq) > > + break; > > + } > > + > > return 0; > > } > > > > -- > > 2.7.4 > > > > > > _______________________________________________ > > linux-arm-kernel mailing list > > linux-arm-kernel@lists.infradead.org > > http://lists.infradead.org/mailman/listinfo/linux-arm-kernel _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel