From: Catalin Marinas <catalin.marinas@arm.com>
To: Marc Zyngier <maz@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
CC Hwang <cc.hwang@mediatek.com>,
Loda Chou <loda.chou@mediatek.com>,
Hanks Chen <hanks.chen@mediatek.com>,
Kuohong Wang <kuohong.wang@mediatek.com>,
Russell King <linux@armlinux.org.uk>,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
Matthias Brugger <matthias.bgg@gmail.com>,
Thomas Gleixner <tglx@linutronix.de>,
Will Deacon <will@kernel.org>,
linux-arm-kernel@lists.infradead.org
Subject: Re: [PATCH v1 1/3] irqchip/gic: enable irq target all
Date: Fri, 27 Nov 2020 18:56:10 +0000 [thread overview]
Message-ID: <20201127185610.GA30096@gaia> (raw)
In-Reply-To: <a3bd54fb5fe1c8ea11559d7459710263@kernel.org>
On Fri, Nov 27, 2020 at 06:11:01PM +0000, Marc Zyngier wrote:
> On 2020-11-27 14:15, Hanks Chen wrote:
> > Support for interrupt distribution design for SMP system solutions.
>
> As far as I know, we have been supporting interrupt distribution on
> ARM SMP systems pretty well for the past... what... 15 years?
> I'm sure Russell can dig out an ARM926 SMP system that even predates
> that.
>
> > With this feature enabled ,the SPI interrupts would be routed to
> > all the cores rather than boot core to achieve better
> > load balance of interrupt handling.
>
> Please quantify this compared to the current distribution method.
>
> > That is, interrupts might be serviced simultaneously on different CPUs.
>
> They already can. What is new here? Or do you mean the *same* interrupt
> being serviced by different CPUs *at the same time*? That'd be fun.
IIRC (it's been many years since I looked at the GIC), more than one CPU
is woken and if they all read the INTACK, only one of them gets the
actual IRQ number, the others see a spurious interrupt. I thought we
decided that's not an efficient way to handle interrupts, so a software
irqbalancer is better.
Has anything changed since then?
I'm also concerned that in a big.LITTLE system, you may see the big CPUs
taking the interrupts all the time, which is nice for energy efficiency.
--
Catalin
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next prev parent reply other threads:[~2020-11-27 18:57 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-27 14:15 Support 1 of N SPI interrupt for interrupt distribution Hanks Chen
2020-11-27 14:15 ` [PATCH v1 1/3] irqchip/gic: enable irq target all Hanks Chen
2020-11-27 18:11 ` Marc Zyngier
2020-11-27 18:56 ` Catalin Marinas [this message]
2020-11-27 19:43 ` Marc Zyngier
2020-12-01 13:54 ` Hanks Chen
2020-12-02 11:09 ` Thomas Gleixner
2020-11-27 14:15 ` [PATCH v1 2/3] arm: disable irq on cpu shutdown flow Hanks Chen
2020-11-27 14:15 ` [PATCH v1 3/3] arm64: " Hanks Chen
2020-11-27 18:27 ` Marc Zyngier
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