From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED,USER_AGENT_SANE_1 autolearn=no autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 09CD0C5519F for ; Fri, 27 Nov 2020 18:57:30 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 9CBD321D7A for ; Fri, 27 Nov 2020 18:57:29 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="cv1623JT" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 9CBD321D7A Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=tD81EGhD3viw18TCQIOlasW1zqC4dbitAhEBfpOOnuc=; b=cv1623JTvw/+1Rr22DIQVRbXi m1brnQP4KuQ+C47ZT3E9DloFrRwzttckMGWhBQK5w1eeysCJx9NROOUnsnST9LGMnDMMDsNG9EjvQ OyjhLqy3W+T44QCFaX//3482axXAFI7oN58DNB0c8ewrYLJEUWUWQuYYfUJjwKUeNotEB1Gfj6kfC gbewsmjdYUNzM8JTSJciMeH+QZMW7aNgzIB1PumuEZHT9WIT0TPthtH1zdO8EgfD8Y8M0OJ2pfqmU p4ZYz89f7bYCahuwkL/GlXcZ9y20wC4Md4XIu0sH41YLFp/p+e9kkEPESFoSWucQJ426WCrpogkb0 w6bdlvkEg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiiup-0001UF-Ab; Fri, 27 Nov 2020 18:56:19 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kiium-0001TK-BK; Fri, 27 Nov 2020 18:56:17 +0000 Received: from gaia (unknown [95.146.230.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 30EE421D7A; Fri, 27 Nov 2020 18:56:13 +0000 (UTC) Date: Fri, 27 Nov 2020 18:56:10 +0000 From: Catalin Marinas To: Marc Zyngier Subject: Re: [PATCH v1 1/3] irqchip/gic: enable irq target all Message-ID: <20201127185610.GA30096@gaia> References: <1606486531-25719-1-git-send-email-hanks.chen@mediatek.com> <1606486531-25719-2-git-send-email-hanks.chen@mediatek.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201127_135616_471538_FCB2AD29 X-CRM114-Status: GOOD ( 17.39 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Mark Rutland , CC Hwang , Loda Chou , Hanks Chen , Kuohong Wang , Russell King , linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org, Matthias Brugger , Thomas Gleixner , Will Deacon , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Fri, Nov 27, 2020 at 06:11:01PM +0000, Marc Zyngier wrote: > On 2020-11-27 14:15, Hanks Chen wrote: > > Support for interrupt distribution design for SMP system solutions. > > As far as I know, we have been supporting interrupt distribution on > ARM SMP systems pretty well for the past... what... 15 years? > I'm sure Russell can dig out an ARM926 SMP system that even predates > that. > > > With this feature enabled ,the SPI interrupts would be routed to > > all the cores rather than boot core to achieve better > > load balance of interrupt handling. > > Please quantify this compared to the current distribution method. > > > That is, interrupts might be serviced simultaneously on different CPUs. > > They already can. What is new here? Or do you mean the *same* interrupt > being serviced by different CPUs *at the same time*? That'd be fun. IIRC (it's been many years since I looked at the GIC), more than one CPU is woken and if they all read the INTACK, only one of them gets the actual IRQ number, the others see a spurious interrupt. I thought we decided that's not an efficient way to handle interrupts, so a software irqbalancer is better. Has anything changed since then? I'm also concerned that in a big.LITTLE system, you may see the big CPUs taking the interrupts all the time, which is nice for energy efficiency. -- Catalin _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel