From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.7 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 59AB4C63777 for ; Mon, 30 Nov 2020 17:14:40 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C66402073C for ; Mon, 30 Nov 2020 17:14:38 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="I7q9ABh8" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C66402073C Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=yjl5HvcUGFF4iF8RHO+HCXDTZrJGofEZmWh1rkAyCpY=; b=I7q9ABh8TYoBmgSPeEzYXrPub mkSaqKgStKwMw1TdDbNhoHsEWQEDEl0h9/apR2EoHuhxbMdSJRAQXkLV1Jh4AeYJP2XFe85521rXf dZzDyxHiMMEOiuxPAI1a2+R+s1JU/6dgICHYELHfFk8IVHCVIKVettQcxBd9voVI7NMdliPDjG9tg uIiySj32Qk+mhZBcamsXvYNfDKbGHi0KgY0CidqTKdXEI4T3Ua2moNaAWzp1R6SZ/Un9uo0lzR1se 3EDBhd9iY89PAU++Gjp16UKDaZ9Ylu97btTSQ/t+pRnloJdQW5+c3+f2WCyqHbzu3kzORpQPjgqbG 0OXS1om5g==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjmjk-0008ET-P0; Mon, 30 Nov 2020 17:13:16 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kjmjh-0008E8-PD for linux-arm-kernel@lists.infradead.org; Mon, 30 Nov 2020 17:13:14 +0000 Received: from gaia (unknown [95.146.230.165]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 133102073C; Mon, 30 Nov 2020 17:13:11 +0000 (UTC) Date: Mon, 30 Nov 2020 17:13:09 +0000 From: Catalin Marinas To: Vincenzo Frascino Subject: Re: [PATCH v2] arm64: mte: Fix typo in macro definition Message-ID: <20201130171309.GG3902@gaia> References: <20201130170709.22309-1-vincenzo.frascino@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201130170709.22309-1-vincenzo.frascino@arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_121313_924926_5E510199 X-CRM114-Status: GOOD ( 19.30 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kasan-dev@googlegroups.com, Will Deacon , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 30, 2020 at 05:07:09PM +0000, Vincenzo Frascino wrote: > UL in the definition of SYS_TFSR_EL1_TF1 was misspelled causing > compilation issues when trying to implement in kernel MTE async > mode. > > Fix the macro correcting the typo. > > Note: MTE async mode will be introduced with a future series. > > Fixes: c058b1c4a5ea ("arm64: mte: system register definitions") > Cc: Catalin Marinas > Cc: Will Deacon > Signed-off-by: Vincenzo Frascino > --- > arch/arm64/include/asm/sysreg.h | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h > index e2ef4c2edf06..801861d05426 100644 > --- a/arch/arm64/include/asm/sysreg.h > +++ b/arch/arm64/include/asm/sysreg.h > @@ -987,7 +987,7 @@ > #define SYS_TFSR_EL1_TF0_SHIFT 0 > #define SYS_TFSR_EL1_TF1_SHIFT 1 > #define SYS_TFSR_EL1_TF0 (UL(1) << SYS_TFSR_EL1_TF0_SHIFT) > -#define SYS_TFSR_EL1_TF1 (UK(2) << SYS_TFSR_EL1_TF1_SHIFT) > +#define SYS_TFSR_EL1_TF1 (UL(1) << SYS_TFSR_EL1_TF1_SHIFT) I think we should first rename it to EU and then fix it properly ;). While nothing breaks without this patch currently, we should merge it as a fix. Acked-by: Catalin Marinas Thanks. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel