From: Mathieu Poirier <mathieu.poirier@linaro.org>
To: Suzuki K Poulose <suzuki.poulose@arm.com>
Cc: al.grant@arm.com, yabinc@google.com, coresight@lists.linaro.org,
Mike Leach <mike.leach@arm.com>,
linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org
Subject: Re: [PATCH] coresight: tmc-etr: Fix barrier packet insertion for perf buffer
Date: Mon, 30 Nov 2020 13:41:48 -0700 [thread overview]
Message-ID: <20201130204148.GD1092947@xps15> (raw)
In-Reply-To: <20201130143602.3450907-1-suzuki.poulose@arm.com>
On Mon, Nov 30, 2020 at 02:36:02PM +0000, Suzuki K Poulose wrote:
> When the ETR is used in perf mode with a larger buffer (configured
> via sysfs or the default size of 1M) than the perf aux buffer size,
> we end up inserting the barrier packet at the wrong offset, while
> moving the offset forward. i.e, instead of the "new moved offset",
> we insert it at the current hardware buffer offset. These packets
> will not be visible as they are never copied and could lead to
> corruption in the trace decoding side, as the decoder is not aware
> that it needs to reset the decoding.
>
> Fixes: ec13c78d7b45 ("coresight: tmc-etr: Add barrier packets when moving offset forward")
> Reported-by: Al Grant <al.grant@arm.com>
> Tested-by: Mike Leach <mike.leach@arm.com>
> Cc: Mathieu Poirier <mathieu.poirier@linaro.org>
> Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
> ---
> drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> index a31a4d7ae25e..bf5230e39c5b 100644
> --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c
> +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c
> @@ -1552,7 +1552,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev,
>
> /* Insert barrier packets at the beginning, if there was an overflow */
> if (lost)
> - tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset);
> + tmc_etr_buf_insert_barrier_packet(etr_buf, offset);
I have applied this patch.
Thanks,
Mathieu
> tmc_etr_sync_perf_buffer(etr_perf, offset, size);
>
> /*
> --
> 2.24.1
>
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prev parent reply other threads:[~2020-11-30 20:43 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-11-30 14:36 [PATCH] coresight: tmc-etr: Fix barrier packet insertion for perf buffer Suzuki K Poulose
2020-11-30 20:41 ` Mathieu Poirier [this message]
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