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[68.147.0.187]) by smtp.gmail.com with ESMTPSA id u3sm17546989pfu.47.2020.11.30.12.41.50 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 30 Nov 2020 12:41:51 -0800 (PST) Date: Mon, 30 Nov 2020 13:41:48 -0700 From: Mathieu Poirier To: Suzuki K Poulose Subject: Re: [PATCH] coresight: tmc-etr: Fix barrier packet insertion for perf buffer Message-ID: <20201130204148.GD1092947@xps15> References: <20201130143602.3450907-1-suzuki.poulose@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201130143602.3450907-1-suzuki.poulose@arm.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201130_154154_545484_38C06A3C X-CRM114-Status: GOOD ( 21.83 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: al.grant@arm.com, yabinc@google.com, coresight@lists.linaro.org, Mike Leach , linux-arm-kernel@lists.infradead.org, mike.leach@linaro.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Mon, Nov 30, 2020 at 02:36:02PM +0000, Suzuki K Poulose wrote: > When the ETR is used in perf mode with a larger buffer (configured > via sysfs or the default size of 1M) than the perf aux buffer size, > we end up inserting the barrier packet at the wrong offset, while > moving the offset forward. i.e, instead of the "new moved offset", > we insert it at the current hardware buffer offset. These packets > will not be visible as they are never copied and could lead to > corruption in the trace decoding side, as the decoder is not aware > that it needs to reset the decoding. > > Fixes: ec13c78d7b45 ("coresight: tmc-etr: Add barrier packets when moving offset forward") > Reported-by: Al Grant > Tested-by: Mike Leach > Cc: Mathieu Poirier > Signed-off-by: Suzuki K Poulose > --- > drivers/hwtracing/coresight/coresight-tmc-etr.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/hwtracing/coresight/coresight-tmc-etr.c b/drivers/hwtracing/coresight/coresight-tmc-etr.c > index a31a4d7ae25e..bf5230e39c5b 100644 > --- a/drivers/hwtracing/coresight/coresight-tmc-etr.c > +++ b/drivers/hwtracing/coresight/coresight-tmc-etr.c > @@ -1552,7 +1552,7 @@ tmc_update_etr_buffer(struct coresight_device *csdev, > > /* Insert barrier packets at the beginning, if there was an overflow */ > if (lost) > - tmc_etr_buf_insert_barrier_packet(etr_buf, etr_buf->offset); > + tmc_etr_buf_insert_barrier_packet(etr_buf, offset); I have applied this patch. Thanks, Mathieu > tmc_etr_sync_perf_buffer(etr_perf, offset, size); > > /* > -- > 2.24.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel