From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.2 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3DAA7C64E7A for ; Tue, 1 Dec 2020 12:16:07 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id BC69720770 for ; Tue, 1 Dec 2020 12:16:06 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="Zr5hxGoP" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org BC69720770 Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=10nIG7VNUq8uJR7QJmjKYoDVL7BPixwMfROGpJTu/nY=; b=Zr5hxGoPimGkQW6zQnsfyUSiC f5/845odHpWuRzC4vnm+lG8DuEz06nEk8lG2/uCNXOyA2CrAnhD79clt8UbYMXnENsslgnmPc6jcX cRYVAzAU+Am1IYF8wOalQaDB81xF6a4grDXalfe2nKtrWoAIjwZRrqjYC/ehDe60vkKEfag4by70I JTDNVneBdoQCu4b8KE4uF3FhJv0YN4nDU5RTCwtF00SkPF/PzHngcXo6ymgGolEU0ONXSsyr/iKml WauP4OrRtCDGZ96nT9XWaOaIjoUZoFbVASoLxQjnRpi8k0+xp7W7b05IrgQpmu7c4+nPVAMk3zb9R 4YCTCts9A==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kk4Yd-00078H-1J; Tue, 01 Dec 2020 12:14:59 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kk4Yb-00077U-C0 for linux-arm-kernel@lists.infradead.org; Tue, 01 Dec 2020 12:14:58 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 7E8C7101E; Tue, 1 Dec 2020 04:14:54 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.30.155]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 887F03F718; Tue, 1 Dec 2020 04:14:50 -0800 (PST) Date: Tue, 1 Dec 2020 12:14:47 +0000 From: Mark Rutland To: James Morse Subject: Re: [PATCHv4 07/17] arm64: sdei: explicitly simulate PAN/UAO entry Message-ID: <20201201121447.GB81672@C02TD0UTHF1T.local> References: <20201113124937.20574-1-mark.rutland@arm.com> <20201113124937.20574-8-mark.rutland@arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201201_071457_480585_3ADCF5A9 X-CRM114-Status: GOOD ( 26.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: catalin.marinas@arm.com, will@kernel.org, hch@lst.de, linux-arm-kernel@lists.infradead.org, robin.murphy@arm.com Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Nov 26, 2020 at 06:42:46PM +0000, James Morse wrote: > Hi Mark, > > On 13/11/2020 12:49, Mark Rutland wrote: > > SDEI enters the kernel with a non-architectural exception which does not > > manipulate PSTATE bits (e.g. PAN, UAO) in the same way as architectural > > exceptions. We currently fix this up with a combination of > > __uaccess_enable_hw_pan() and force_uaccess_access_begin(), but this has > > a few problems: > > > > * When set_fs() is removed, force_uaccess_begin() will have no HW > > side-effects, and UAO will need to be reset elsewhere. > > > > * Kernels built without support for PAN or UAO will not reset these bits > > upon SDEI entry, and may inherit the values used by a VM, leading to > > unexpected behaviour. > > > > * Kernels built *with* support for PAN or UAO, when run on systems with > > mismatched support across CPUs, will not reset these bits upon SDEI > > entry, and may inherit the values used by a VM, leading to unexpected > > behaviour. > > > To deal with all of these, let's always explicitly reset the PAN and UAO > > bits when an SDEI event is delivered to the kernel. As above, we must do > > so even when the kernel has chosen to not use PAN/UAO, or was not built > > with support for PAN/UAO generally. > > > > The existing system_uses_ttbr0_pan() is redefined in terms of > > system_uses_hw_pan() both for clarity and as a minor optimization when > > HW PAN is not selected. > > Reviewed-by: James Morse Thanks! Per the comments on patch 14, I've reworked this to remove the UAO bits (and correspondingly, have rewritten the commit message), so I'll post v5 without your R-b just in case there's anything objectionable in that rework. > > diff --git a/arch/arm64/kernel/sdei.c b/arch/arm64/kernel/sdei.c > > index 4a5f24602aa0..908d7be70eac 100644 > > --- a/arch/arm64/kernel/sdei.c > > +++ b/arch/arm64/kernel/sdei.c > > @@ -224,12 +234,11 @@ __sdei_handler(struct pt_regs *regs, struct sdei_registered_event *arg) > > mm_segment_t orig_addr_limit; > > > > /* > > - * We didn't take an exception to get here, so the HW hasn't set PAN or > > - * cleared UAO, and the exception entry code hasn't reset addr_limit. > > - * Set PAN, then use force_uaccess_begin() to clear UAO and reset > > - * addr_limit. > > + * We didn't take an exception to get here, so the HW hasn't > > + * set/cleared bits in PSTATE that we may rely on. Intialize PAN/UAO, > > (Initialize) Whoops, fixed. Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel