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[84.226.167.205]) by smtp.googlemail.com with ESMTPSA id k17sm378283ejj.1.2020.12.02.09.34.07 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 02 Dec 2020 09:34:07 -0800 (PST) Date: Wed, 2 Dec 2020 19:34:05 +0200 From: Krzysztof Kozlowski To: Jagan Teki Subject: Re: [PATCH 04/10] arm64: dts: imx8mm: Add Engicam i.Core MX8M Mini SOM Message-ID: <20201202173405.GD3490@kozik-lap> References: <20201202121241.109952-1-jagan@amarulasolutions.com> <20201202121241.109952-5-jagan@amarulasolutions.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201202121241.109952-5-jagan@amarulasolutions.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201202_123410_390253_56DF3670 X-CRM114-Status: GOOD ( 23.15 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Matteo Lisi , Shawn Guo , linux-kernel@vger.kernel.org, Li Yang , Rob Herring , NXP Linux Team , Fabio Estevam , linux-amarula@amarulasolutions.com, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 02, 2020 at 05:42:35PM +0530, Jagan Teki wrote: > i.Core MX8M Mini is an EDIMM SOM based on NXP i.MX8MM from Engicam. s/SOM/SoM/ > > General features: > - NXP i.MX8MM i.MX 8M Mini as named by NXP: https://www.nxp.com/products/processors-and-microcontrollers/arm-processors/i-mx-applications-processors/i-mx-8-processors/i-mx-8m-mini-arm-cortex-a53-cortex-m4-audio-voice-video:i.MX8MMINI > - Up to 2GB LDDR4 > - 8/16GB eMMC > - Gigabit Ethernet > - USB 2.0 Host/OTG > - PCIe Gen2 interface > - I2S > - MIPI DSI to LVDS > - rest of i.MX8MM features Ditto > > i.Core MX8M Mini needs to mount on top of Engicam baseboards for > creating complete platform boards. > > Possible baseboards are, > - EDIMM2.2 > - C.TOUCH 2.0 Don't describe baseboards. You add here only SoM. > > Add support for it. > > Signed-off-by: Matteo Lisi > Signed-off-by: Jagan Teki > --- > .../freescale/imx8mm-engicam-icore-mx8mm.dtsi | 209 ++++++++++++++++++ > 1 file changed, 209 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > new file mode 100644 > index 000000000000..b87917c40587 > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-engicam-icore-mx8mm.dtsi > @@ -0,0 +1,209 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright (c) 2018 NXP > + * Copyright (c) 2019 Engicam srl > + * Copyright (c) 2020 Amarula Solutons(India) > + */ > + > +/ { Missing "model". > + compatible = "engicam,icore-mx8mm", "fsl,imx8mm"; > +}; > + No memory node? Isn't the memory a property of SoM? > +&A53_0 { > + cpu-supply = <®_buck4>; > +}; Supplies for the other cores. > + > +&i2c1 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c1>; > + status = "okay"; > + > + pf8100@8 { Node name should describe generic class of a device, so probably you wanted here "pmic". > + compatible = "nxp,pf8x00"; > + reg = <0x08>; > + > + regulators { > + reg_ldo1: ldo1 { > + regulator-always-on; > + regulator-boot-on; First min/max constraints. Then always-on and boot-on properties. > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo2: ldo2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo3: ldo3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_ldo4: ldo4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <5000000>; > + regulator-min-microvolt = <1500000>; > + }; > + > + reg_buck1: buck1 { > + fsl,ilim-ma = <4500>; Where is this property documented? > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck2: buck2 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck3: buck3 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck4: buck4 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + fast-slew = <1>; Where is this property documented? > + }; > + > + reg_buck5: buck5 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck6: buck6 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <1800000>; > + regulator-min-microvolt = <400000>; > + }; > + > + reg_buck7: buck7 { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <3300000>; > + }; > + > + reg_vsnvs: vsnvs { > + regulator-always-on; > + regulator-boot-on; > + regulator-max-microvolt = <3300000>; > + regulator-min-microvolt = <1800000>; > + }; > + }; > + }; > +}; > + > +&iomuxc { > + pinctrl_i2c1: i2c1grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C1_SCL_I2C1_SCL 0x400001c3 > + MX8MM_IOMUXC_I2C1_SDA_I2C1_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_uart2: uart2grp { Not used. > + fsl,pins = < > + MX8MM_IOMUXC_UART2_RXD_UART2_DCE_RX 0x140 > + MX8MM_IOMUXC_UART2_TXD_UART2_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_usdhc1_gpio: usdhc1grpgpio { This should complain on bindings check. Please run dtbs_check. The "grp" should be a suffix in node name, so "usdhc1gpiogrp". > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x41 > + >; > + }; > + > + pinctrl_usdhc1: usdhc1grp { Not used. Best regards, Krzysztof _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel