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spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=AZVo+cIMeTqg5t0remlZTwslXO2fpx4HE4IfBpWoJos=; b=Afj+emYq0zFc9JooH+BHr5sho 826JHenoJZR04RY1wbbgboR8LuOTt5aEAQmMhlq8pdRC0AqgpddAXkYsoF91n5iUSweaxpT/q564M 0l1zowy0/wK7Hpq2FquHOWvu79t4KW1L5p1b3QdqmqTmS4ogiWl2xADOFXOkcwKNRVUzQbT4F9m5b 6kKhrQ2rWHEwRhGk9dEVPm/dxhzyaUEUKMn0/Invg47xG235Yaktw2AQyqn3SSjIjuDeGGIXqM2zX qBafI/ob/jGTX2OMIySz62EPq/fG2M4mN+x+wGw0oV6woLDNqZBsY3u2u8ptfcmyzb6BShPz5Bq5V Xw+4cMsjQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkW9L-0006Wd-79; Wed, 02 Dec 2020 17:42:43 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kkW9I-0006Vb-67 for linux-arm-kernel@lists.infradead.org; Wed, 02 Dec 2020 17:42:41 +0000 Date: Wed, 2 Dec 2020 17:42:31 +0000 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=default; t=1606930959; bh=D2qJHiLr3WBE8qC72MiAMFHT38KmW7506TfoTHNti9c=; h=From:To:Cc:Subject:References:In-Reply-To:From; b=i05isdxBRqIaUgFl3BpQMh2hiXe2kAlVAF+dzOTJ7GD8dpUYkdVRihIUN5Hnp5Qk3 0yYy7thXReJ5Cu2+cXIUf8f8bbgGbzOQaE82RcX4OmcdpeYfH2ttlTc1SplwfIH5Ow TZaXg1vsuOSO/7oFUF2Cb77LRSnSw/JOuWtrGA1Q= From: Will Deacon To: Qais Yousef Subject: Re: [PATCH v4 12/14] arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system Message-ID: <20201202174230.GA29939@willie-the-truck> References: <20201124155039.13804-1-will@kernel.org> <20201124155039.13804-13-will@kernel.org> <20201127134122.oughqeizhl2j4iky@e107158-lin.cambridge.arm.com> <20201201221335.GA28496@willie-the-truck> <20201202125952.z2q6oucoqbwt6aq2@e107158-lin.cambridge.arm.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201202125952.z2q6oucoqbwt6aq2@e107158-lin.cambridge.arm.com> User-Agent: Mutt/1.10.1 (2018-07-13) X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201202_124240_372357_04A5FC53 X-CRM114-Status: GOOD ( 21.53 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Vincent Guittot , Juri Lelli , Quentin Perret , Peter Zijlstra , Catalin Marinas , Johannes Weiner , linux-kernel@vger.kernel.org, Ingo Molnar , Li Zefan , Greg Kroah-Hartman , Tejun Heo , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 02, 2020 at 12:59:52PM +0000, Qais Yousef wrote: > On 12/01/20 22:13, Will Deacon wrote: > > On Fri, Nov 27, 2020 at 01:41:22PM +0000, Qais Yousef wrote: > > > On 11/24/20 15:50, Will Deacon wrote: > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > > index 29017cbb6c8e..fe470683b43e 100644 > > > > --- a/arch/arm64/kernel/cpufeature.c > > > > +++ b/arch/arm64/kernel/cpufeature.c > > > > @@ -1237,6 +1237,8 @@ has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > > > static int enable_mismatched_32bit_el0(unsigned int cpu) > > > > { > > > > + static int lucky_winner = -1; > > > > + > > > > struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > > > > bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > > > > > > > > @@ -1245,6 +1247,22 @@ static int enable_mismatched_32bit_el0(unsigned int cpu) > > > > static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); > > > > } > > > > > > > > + if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) > > > > + return 0; > > > > > > Hmm I'm struggling to get what you're doing here. You're treating CPU0 (the > > > boot CPU) specially here, but I don't get why? > > > > If our ability to execute 32-bit code is the same as the boot CPU then we > > don't have to do anything. That way, we can postpone nominating the lucky > > winner until we really need to. > > Okay I see what you're doing now. The '== cpu_32bit' part of the check gave me > trouble. If the first N cpus are 64bit only, we'll skip them here. Worth > a comment? > > Wouldn't it be better to replace this with a check if cpu_32bit_el0_mask is > empty instead? That would be a lot easier to read. Sorry, but I don't follow. What if all the CPUs are 32-bit capable? I'll leave the code as-is, since I don't think it's particularly hard to understand, and it does the right thing. Will _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel