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From: Suzuki K Poulose <suzuki.poulose@arm.com>
To: linux-arm-kernel@lists.infradead.org
Cc: mathieu.poirier@linaro.org,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	catalin.marinas@arm.com, linux-kernel@vger.kernel.org,
	leo.yan@linaro.org, jonathan.zhouwen@huawei.com,
	mike.leach@linaro.org
Subject: [PATCH v5 17/25] coresight: etm4x: Use TRCDEVARCH for component discovery
Date: Mon, 14 Dec 2020 17:37:23 +0000	[thread overview]
Message-ID: <20201214173731.302520-18-suzuki.poulose@arm.com> (raw)
In-Reply-To: <20201214173731.302520-1-suzuki.poulose@arm.com>

We have been using TRCIDR1 for detecting the ETM version. This
is in preparation for the future IP support.

Cc: Mike Leach <mike.leach@linaro.org>
Reviewed-by: Mathieu Poirier <mathieu.poirier@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
---
 .../coresight/coresight-etm4x-core.c          | 46 +++++++++----------
 1 file changed, 23 insertions(+), 23 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm4x-core.c b/drivers/hwtracing/coresight/coresight-etm4x-core.c
index 55d8f1b9219b..128390f9b7fd 100644
--- a/drivers/hwtracing/coresight/coresight-etm4x-core.c
+++ b/drivers/hwtracing/coresight/coresight-etm4x-core.c
@@ -150,18 +150,6 @@ static void etm4_cs_unlock(struct etmv4_drvdata *drvdata,
 		CS_UNLOCK(csa->base);
 }
 
-static bool etm4_arch_supported(u8 arch)
-{
-	/* Mask out the minor version number */
-	switch (arch & 0xf0) {
-	case ETM_ARCH_V4:
-		break;
-	default:
-		return false;
-	}
-	return true;
-}
-
 static int etm4_cpu_id(struct coresight_device *csdev)
 {
 	struct etmv4_drvdata *drvdata = dev_get_drvdata(csdev->dev.parent);
@@ -686,6 +674,26 @@ static const struct coresight_ops etm4_cs_ops = {
 static bool etm4_init_iomem_access(struct etmv4_drvdata *drvdata,
 				   struct csdev_access *csa)
 {
+	u32 devarch = readl_relaxed(drvdata->base + TRCDEVARCH);
+	u32 idr1 = readl_relaxed(drvdata->base + TRCIDR1);
+
+	/*
+	 * All ETMs must implement TRCDEVARCH to indicate that
+	 * the component is an ETMv4. To support any broken
+	 * implementations we fall back to TRCIDR1 check, which
+	 * is not really reliable.
+	 */
+	if ((devarch & ETM_DEVARCH_ID_MASK) == ETM_DEVARCH_ETMv4x_ARCH) {
+		drvdata->arch = etm_devarch_to_arch(devarch);
+	} else {
+		pr_warn("CPU%d: ETM4x incompatible TRCDEVARCH: %x, falling back to TRCIDR1\n",
+			smp_processor_id(), devarch);
+
+		if (ETM_TRCIDR1_ARCH_MAJOR(idr1) != ETM_TRCIDR1_ARCH_ETMv4)
+			return false;
+		drvdata->arch = etm_trcidr_to_arch(idr1);
+	}
+
 	*csa = CSDEV_ACCESS_IOMEM(drvdata->base);
 	return true;
 }
@@ -702,7 +710,6 @@ static bool etm4_init_csdev_access(struct etmv4_drvdata *drvdata,
 static void etm4_init_arch_data(void *info)
 {
 	u32 etmidr0;
-	u32 etmidr1;
 	u32 etmidr2;
 	u32 etmidr3;
 	u32 etmidr4;
@@ -767,14 +774,6 @@ static void etm4_init_arch_data(void *info)
 	/* TSSIZE, bits[28:24] Global timestamp size field */
 	drvdata->ts_size = BMVAL(etmidr0, 24, 28);
 
-	/* base architecture of trace unit */
-	etmidr1 = etm4x_relaxed_read32(csa, TRCIDR1);
-	/*
-	 * TRCARCHMIN, bits[7:4] architecture the minor version number
-	 * TRCARCHMAJ, bits[11:8] architecture major versin number
-	 */
-	drvdata->arch = BMVAL(etmidr1, 4, 11);
-
 	/* maximum size of resources */
 	etmidr2 = etm4x_relaxed_read32(csa, TRCIDR2);
 	/* CIDSIZE, bits[9:5] Indicates the Context ID size */
@@ -1614,7 +1613,7 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 				etm4_init_arch_data,  &init_arg, 1))
 		dev_err(dev, "ETM arch init failed\n");
 
-	if (etm4_arch_supported(drvdata->arch) == false)
+	if (!drvdata->arch)
 		return -EINVAL;
 
 	etm4_init_trace_id(drvdata);
@@ -1646,7 +1645,8 @@ static int etm4_probe(struct amba_device *adev, const struct amba_id *id)
 
 	pm_runtime_put(&adev->dev);
 	dev_info(&drvdata->csdev->dev, "CPU%d: ETM v%d.%d initialized\n",
-		 drvdata->cpu, drvdata->arch >> 4, drvdata->arch & 0xf);
+		 drvdata->cpu, ETM_ARCH_MAJOR_VERSION(drvdata->arch),
+		 ETM_ARCH_MINOR_VERSION(drvdata->arch));
 
 	if (boot_enable) {
 		coresight_enable(drvdata->csdev);
-- 
2.24.1


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  parent reply	other threads:[~2020-12-14 17:43 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2020-12-14 17:37 [PATCH v5 00/25] coresight: etm4x: Support for system instructions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 01/25] coresight: etm4x: Handle access to TRCSSPCICRn Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 02/25] coresight: etm4x: Skip accessing TRCPDCR in save/restore Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 03/25] coresight: Introduce device access abstraction Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 04/25] coresight: tpiu: Prepare for using coresight " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 05/25] coresight: Convert coresight_timeout to use " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 06/25] coresight: Convert claim/disclaim operations to use access wrappers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 07/25] coresight: etm4x: Always read the registers on the host CPU Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 08/25] coresight: etm4x: Convert all register accesses Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 09/25] coresight: etm4x: Add commentary on the registers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 10/25] coresight: etm4x: Add sysreg access helpers Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 11/25] coresight: etm4x: Define DEVARCH register fields Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 12/25] coresight: etm4x: Check for Software Lock Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 13/25] coresight: etm4x: Cleanup secure exception level masks Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 14/25] coresight: etm4x: Clean up " Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 15/25] coresight: etm4x: Handle ETM architecture version Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 16/25] coresight: etm4x: Detect access early on the target CPU Suzuki K Poulose
2020-12-14 17:37 ` Suzuki K Poulose [this message]
2020-12-14 17:37 ` [PATCH v5 18/25] coresight: etm4x: Expose trcdevarch via trcidr Suzuki K Poulose
2020-12-16 18:01   ` Mike Leach
2020-12-14 17:37 ` [PATCH v5 19/25] coresight: etm4x: Add necessary synchronization for sysreg access Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 20/25] coresight: etm4x: Detect system instructions support Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 21/25] coresight: etm4x: Refactor probing routine Suzuki K Poulose
2021-01-05 21:44   ` Mathieu Poirier
2020-12-14 17:37 ` [PATCH v5 22/25] coresight: etm4x: Add support for sysreg only devices Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 23/25] dts: bindings: coresight: ETM system register access only units Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 24/25] arm64: Add TRFCR_ELx definitions Suzuki K Poulose
2020-12-14 17:37 ` [PATCH v5 25/25] coresight: Add support for v8.4 SelfHosted tracing Suzuki K Poulose
2021-01-06 14:48 ` [PATCH v5 00/25] coresight: etm4x: Support for system instructions Mike Leach
2021-01-06 14:52   ` Suzuki K Poulose

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