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Tue, 15 Dec 2020 17:36:48 +0000 Received: from hirez.programming.kicks-ass.net (hirez.programming.kicks-ass.net [192.168.1.225]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (Client did not present a certificate) by noisy.programming.kicks-ass.net (Postfix) with ESMTPS id 6B6BD3070AB; Tue, 15 Dec 2020 18:36:45 +0100 (CET) Received: by hirez.programming.kicks-ass.net (Postfix, from userid 1000) id 4F432203EE86F; Tue, 15 Dec 2020 18:36:45 +0100 (CET) Date: Tue, 15 Dec 2020 18:36:45 +0100 From: Peter Zijlstra To: Will Deacon Subject: Re: [PATCH v5 00/15] An alternative series for asymmetric AArch32 systems Message-ID: <20201215173645.GJ3040@hirez.programming.kicks-ass.net> References: <20201208132835.6151-1-will@kernel.org> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201208132835.6151-1-will@kernel.org> X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arch@vger.kernel.org, Marc Zyngier , kernel-team@android.com, Vincent Guittot , Juri Lelli , Quentin Perret , Catalin Marinas , Johannes Weiner , linux-kernel@vger.kernel.org, Qais Yousef , Ingo Molnar , Li Zefan , Greg Kroah-Hartman , Tejun Heo , Suren Baghdasaryan , Morten Rasmussen , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 08, 2020 at 01:28:20PM +0000, Will Deacon wrote: > The aim of this series is to allow 32-bit ARM applications to run on > arm64 SoCs where not all of the CPUs support the 32-bit instruction set. > Unfortunately, such SoCs are real and will continue to be productised > over the next few years at least. I can assure you that I'm not just > doing this for fun. > > Changes in v5 include: > > * Teach cpuset_cpus_allowed() about task_cpu_possible_mask() so that > we can avoid returning incompatible CPUs for a given task. This > means that sched_setaffinity() can be used with larger masks (like > the online mask) from userspace and also allows us to take into > account the cpuset hierarchy when forcefully overriding the affinity > for a task on execve(). > > * Honour task_cpu_possible_mask() when attaching a task to a cpuset, > so that the resulting affinity mask does not contain any incompatible > CPUs (since it would be rejected by set_cpus_allowed_ptr() otherwise). > > * Moved overriding of the affinity mask into the scheduler core rather > than munge affinity masks directly in the architecture backend. Hurmph... so if I can still read, this thing will auto truncate the affinity mask to something that only contains compatible CPUs, right? Assuming our system has 8 CPUs (0xFF), half of which are 32bit capable (0x0F), then, when our native task (with affinity 0x3c) does a fork()+execve() of a 32bit thingy the resulting task has 0x0c. If that in turn does fork()+execve() of a native task, it will retain the trucated affinity mask (0x0c), instead of returning to the wider mask (0x3c). IOW, any (accidental or otherwise) trip through a 32bit helper, will destroy user state (the affinity mask: 0x3c). Should we perhaps split task_struct::cpus_mask, one to keep an original copy of the user state, and one to be an effective cpumask for the task? That way, the moment a task constricts or widens it's task_cpu_possible_mask() we can re-compute the effective mask without loss of information. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel