From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,INCLUDES_CR_TRAILER,INCLUDES_PATCH,MAILING_LIST_MULTI, SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 69A84C4361B for ; Tue, 15 Dec 2020 23:32:05 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EBA42217BA for ; Tue, 15 Dec 2020 23:32:04 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org EBA42217BA Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=kernel.org Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Message-ID:Subject:To:From: Date:Reply-To:Content-ID:Content-Description:Resent-Date:Resent-From: Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:References:List-Owner; bh=eKb1IPDpvCRGzN8kFcy/29E0Olq33XuzUxqHk0C5UWI=; b=ZkDJXSMMmy6Ir7u5sJClwFuwd 1zCMovLWO8wKYZd0KBzNzSPcHKDYMXebUZkMSeDx5wGLRJHEPtem5JiEUEh7vD13qfT1ewv2N/AFS Sea4j/fCYLiVTrTU/4WHq5HzWB7EupHiCj/75MN8Z/Ue7LYFypIg0k4nxFJlJc/KPIQW7QEW4cfn3 2W6DQWgUUwCG0P82r54VcPUaQkTzGiz7gfkAExvj/bXsf7YQYTIl6UBSRtz1z4DctUv+DLa4Z19g4 oNo+ELOEt2CDBStEcL9t5IcY87bqsuGEQFfL638VSLhZZu1nSn5bTuAARShCBzWibWCzJRPGYwL7f 1Wz9Txmxw==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kpJm6-0000ax-GA; Tue, 15 Dec 2020 23:30:34 +0000 Received: from mail.kernel.org ([198.145.29.99]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kpJm3-0000aa-It for linux-arm-kernel@lists.infradead.org; Tue, 15 Dec 2020 23:30:32 +0000 Date: Tue, 15 Dec 2020 17:30:28 -0600 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1608075030; bh=G4W+JOW70+nhdR5jB10BduQ3Oi8mabagk8z9ckwebGU=; h=From:To:Cc:Subject:In-Reply-To:From; b=mtKceyn6b2eHbktRbWzKjS/6cyF9pUzW7ZlfheuX4mKS/3K0iVp4Fo5GXObuIqNk7 znMb2I7vpO9r9wyvisEF/6kt7FazkDUsKQI73UWeLdAQJYcioiGChQViMD991ie5pY 0rphB9CT8NrO05jvpD7V1uISvt9/Vu9rr7VZ77tn3NS8vLg0eSbjTc3rCG5Zb192Lz ZJrZg1oJzU16+mwuCDq1BNPKAQKt9PsIcvE8KFYnA88Imi8Kep1kFE68w/BTVD4Cfz eL4bD5DNu76ltavi4L91n3AYoUwHBgNPJjAwrs5c2LDj51t/N4DGyWZzuOxZGtUcNL W331xVqJkdmug== From: Bjorn Helgaas To: Kishon Vijay Abraham I Subject: Re: [PATCH v5] PCI: cadence: Retrain Link to work around Gen2 training defect. Message-ID: <20201215233028.GA336802@bjorn-Precision-5520> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20201215070009.27937-1-kishon@ti.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201215_183031_770376_23BDBCFB X-CRM114-Status: GOOD ( 32.12 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Rob Herring , Nadeem Athani , mparab@cadence.com, linux-pci@vger.kernel.org, pthombar@cadence.com, linux-kernel@vger.kernel.org, Tom Joseph , sjakhade@cadence.com, Bjorn Helgaas , linux-omap@vger.kernel.org, linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Tue, Dec 15, 2020 at 12:30:09PM +0530, Kishon Vijay Abraham I wrote: > From: Nadeem Athani > > Cadence controller will not initiate autonomous speed change if strapped as > Gen2. The Retrain Link bit is set as quirk to enable this speed change. > > Signed-off-by: Nadeem Athani > [kishon@ti.com: Enable the workaround for TI's J721E SoC] > Signed-off-by: Kishon Vijay Abraham I > --- > Hi Lorenzo, > The previous version of the patch can be found at [1]. > I slightly re-worked the patch from Nadeem > *) Removed additional Link Up Check > *) Removed quirk from pcie-cadence-plat.c > *) Also removed additional compatible > "cdns,cdns-pcie-host-quirk-retrain" added in that series > *) Enabled the quirk for J721E > [1] -> http://lore.kernel.org/r/20201211144236.3825-1-nadeem@cadence.com > > drivers/pci/controller/cadence/pci-j721e.c | 3 + > .../controller/cadence/pcie-cadence-host.c | 67 ++++++++++++++----- > drivers/pci/controller/cadence/pcie-cadence.h | 11 ++- > 3 files changed, 62 insertions(+), 19 deletions(-) > > diff --git a/drivers/pci/controller/cadence/pci-j721e.c b/drivers/pci/controller/cadence/pci-j721e.c > index dac1ac8a7615..baf729850cb1 100644 > --- a/drivers/pci/controller/cadence/pci-j721e.c > +++ b/drivers/pci/controller/cadence/pci-j721e.c > @@ -64,6 +64,7 @@ enum j721e_pcie_mode { > > struct j721e_pcie_data { > enum j721e_pcie_mode mode; > + bool quirk_retrain_flag; > }; > > static inline u32 j721e_pcie_user_readl(struct j721e_pcie *pcie, u32 offset) > @@ -280,6 +281,7 @@ static struct pci_ops cdns_ti_pcie_host_ops = { > > static const struct j721e_pcie_data j721e_pcie_rc_data = { > .mode = PCI_MODE_RC, > + .quirk_retrain_flag = true, > }; > > static const struct j721e_pcie_data j721e_pcie_ep_data = { > @@ -388,6 +390,7 @@ static int j721e_pcie_probe(struct platform_device *pdev) > > bridge->ops = &cdns_ti_pcie_host_ops; > rc = pci_host_bridge_priv(bridge); > + rc->quirk_retrain_flag = data->quirk_retrain_flag; > > cdns_pcie = &rc->pcie; > cdns_pcie->dev = dev; > diff --git a/drivers/pci/controller/cadence/pcie-cadence-host.c b/drivers/pci/controller/cadence/pcie-cadence-host.c > index 811c1cb2e8de..773c0d1137ed 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence-host.c > +++ b/drivers/pci/controller/cadence/pcie-cadence-host.c > @@ -77,6 +77,50 @@ static struct pci_ops cdns_pcie_host_ops = { > .write = pci_generic_config_write, > }; > > +static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) > +{ > + struct device *dev = pcie->dev; > + int retries; > + > + /* Check if the link is up or not */ > + for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { > + if (cdns_pcie_link_up(pcie)) { - cdns_pcie_link_up() always returns "true" except for j721e_pcie_ops. Is it really true that we can assume the link is up otherwise? - Where did the LINK_WAIT_* values come from? Are they derived from something in the PCIe spec? - Is the LINK_WAIT timeout related to LINK_RETRAIN_TIMEOUT? - If the PCI core does a link retrain, e.g., in pcie_retrain_link(), does that work correctly on this device? [I see now that this patch only *moves* this code without changing it. But I'm still curious.] > + dev_info(dev, "Link up\n"); > + return 0; > + } > + usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); > + } > + > + return -ETIMEDOUT; > +} > + > +static void cdns_pcie_retrain(struct cdns_pcie *pcie) > +{ > + u32 lnk_cap_sls, pcie_cap_off = CDNS_PCIE_RP_CAP_OFFSET; > + u16 lnk_stat, lnk_ctl; > + > + /* > + * Set retrain bit if current speed is 2.5 GB/s, > + * but the PCIe root port support is > 2.5 GB/s. > + */ > + > + lnk_cap_sls = cdns_pcie_readl(pcie, (CDNS_PCIE_RP_BASE + pcie_cap_off + > + PCI_EXP_LNKCAP)); > + if ((lnk_cap_sls & PCI_EXP_LNKCAP_SLS) <= PCI_EXP_LNKCAP_SLS_2_5GB) > + return; > + > + lnk_stat = cdns_pcie_rp_readw(pcie, pcie_cap_off + PCI_EXP_LNKSTA); > + if ((lnk_stat & PCI_EXP_LNKSTA_CLS) == PCI_EXP_LNKSTA_CLS_2_5GB) { > + lnk_ctl = cdns_pcie_rp_readw(pcie, > + pcie_cap_off + PCI_EXP_LNKCTL); > + lnk_ctl |= PCI_EXP_LNKCTL_RL; > + cdns_pcie_rp_writew(pcie, pcie_cap_off + PCI_EXP_LNKCTL, > + lnk_ctl); > + > + if (cdns_pcie_host_wait_for_link(pcie)) > + return; > + } > +} > > static int cdns_pcie_host_init_root_port(struct cdns_pcie_rc *rc) > { > @@ -398,23 +442,6 @@ static int cdns_pcie_host_init(struct device *dev, > return cdns_pcie_host_init_address_translation(rc); > } > > -static int cdns_pcie_host_wait_for_link(struct cdns_pcie *pcie) > -{ > - struct device *dev = pcie->dev; > - int retries; > - > - /* Check if the link is up or not */ > - for (retries = 0; retries < LINK_WAIT_MAX_RETRIES; retries++) { > - if (cdns_pcie_link_up(pcie)) { > - dev_info(dev, "Link up\n"); > - return 0; > - } > - usleep_range(LINK_WAIT_USLEEP_MIN, LINK_WAIT_USLEEP_MAX); > - } > - > - return -ETIMEDOUT; > -} This piece looks like a pure move of cdns_pcie_host_wait_for_link() with no other changes. It would be nicer to split that to a separate patch so it doesn't obscure what's really happening in this patch. > int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) > { > struct device *dev = rc->pcie.dev; > @@ -458,8 +485,12 @@ int cdns_pcie_host_setup(struct cdns_pcie_rc *rc) > } > > ret = cdns_pcie_host_wait_for_link(pcie); > - if (ret) > + if (ret) { > dev_dbg(dev, "PCIe link never came up\n"); > + } else { > + if (rc->quirk_retrain_flag) > + cdns_pcie_retrain(pcie); > + } > > for (bar = RP_BAR0; bar <= RP_NO_BAR; bar++) > rc->avail_ib_bar[bar] = true; > diff --git a/drivers/pci/controller/cadence/pcie-cadence.h b/drivers/pci/controller/cadence/pcie-cadence.h > index 30eba6cafe2c..0f29128a5d0a 100644 > --- a/drivers/pci/controller/cadence/pcie-cadence.h > +++ b/drivers/pci/controller/cadence/pcie-cadence.h > @@ -119,7 +119,7 @@ > * Root Port Registers (PCI configuration space for the root port function) > */ > #define CDNS_PCIE_RP_BASE 0x00200000 > - > +#define CDNS_PCIE_RP_CAP_OFFSET 0xc0 > > /* > * Address Translation Registers > @@ -291,6 +291,7 @@ struct cdns_pcie { > * @device_id: PCI device ID > * @avail_ib_bar: Satus of RP_BAR0, RP_BAR1 and RP_NO_BAR if it's free or > * available > + * @quirk_retrain_flag: Retrain link as quirk for PCIe Gen2 > */ > struct cdns_pcie_rc { > struct cdns_pcie pcie; > @@ -299,6 +300,7 @@ struct cdns_pcie_rc { > u32 vendor_id; > u32 device_id; > bool avail_ib_bar[CDNS_PCIE_RP_MAX_IB]; > + bool quirk_retrain_flag; > }; > > /** > @@ -414,6 +416,13 @@ static inline void cdns_pcie_rp_writew(struct cdns_pcie *pcie, > cdns_pcie_write_sz(addr, 0x2, value); > } > > +static inline u16 cdns_pcie_rp_readw(struct cdns_pcie *pcie, u32 reg) > +{ > + void __iomem *addr = pcie->reg_base + CDNS_PCIE_RP_BASE + reg; > + > + return cdns_pcie_read_sz(addr, 0x2); > +} > + > /* Endpoint Function register access */ > static inline void cdns_pcie_ep_fn_writeb(struct cdns_pcie *pcie, u8 fn, > u32 reg, u8 value) > -- > 2.17.1 > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel