From: Kishon Vijay Abraham I <kishon@ti.com>
To: Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Swapnil Jakhade <sjakhade@cadence.com>,
<linux-kernel@vger.kernel.org>, <devicetree@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>
Cc: Nishanth Menon <nm@ti.com>, Philipp Zabel <p.zabel@pengutronix.de>
Subject: [PATCH v2 10/14] phy: cadence: sierra: Enable pll_cmnlc and pll_cmnlc1 clocks
Date: Tue, 22 Dec 2020 12:35:16 +0530 [thread overview]
Message-ID: <20201222070520.28132-11-kishon@ti.com> (raw)
In-Reply-To: <20201222070520.28132-1-kishon@ti.com>
Get pll_cmnlc and pll_cmnlc1 optional clocks and enable them.
This will enable REFRCV/1 in case the pll_cmnlc/1 takes input
from REFRCV/1 respectively.
Signed-off-by: Kishon Vijay Abraham I <kishon@ti.com>
---
drivers/phy/cadence/phy-cadence-sierra.c | 56 +++++++++++++++++++++++-
1 file changed, 54 insertions(+), 2 deletions(-)
diff --git a/drivers/phy/cadence/phy-cadence-sierra.c b/drivers/phy/cadence/phy-cadence-sierra.c
index 2a509be80c80..553971683f2d 100644
--- a/drivers/phy/cadence/phy-cadence-sierra.c
+++ b/drivers/phy/cadence/phy-cadence-sierra.c
@@ -267,6 +267,8 @@ struct cdns_sierra_phy {
struct clk *clk;
struct clk *cmn_refclk_dig_div;
struct clk *cmn_refclk1_dig_div;
+ struct clk *pll_cmnlc;
+ struct clk *pll_cmnlc1;
int nsubnodes;
u32 num_lanes;
bool autoconf;
@@ -874,9 +876,59 @@ static int cdns_sierra_phy_get_clocks(struct cdns_sierra_phy *sp,
}
sp->cmn_refclk1_dig_div = clk;
+ clk = devm_clk_get_optional(dev, "pll_cmnlc");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc = clk;
+
+ clk = devm_clk_get_optional(dev, "pll_cmnlc1");
+ if (IS_ERR(clk)) {
+ dev_err(dev, "pll_cmnlc1 clock not found\n");
+ ret = PTR_ERR(clk);
+ return ret;
+ }
+ sp->pll_cmnlc1 = clk;
+
return 0;
}
+static int cdns_sierra_phy_enable_clocks(struct cdns_sierra_phy *sp)
+{
+ int ret;
+
+ ret = clk_prepare_enable(sp->clk);
+ if (ret)
+ return ret;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc);
+ if (ret)
+ goto err_pll_cmnlc;
+
+ ret = clk_prepare_enable(sp->pll_cmnlc1);
+ if (ret)
+ goto err_pll_cmnlc1;
+
+ return 0;
+
+err_pll_cmnlc:
+ clk_disable_unprepare(sp->clk);
+
+err_pll_cmnlc1:
+ clk_disable_unprepare(sp->pll_cmnlc);
+
+ return 0;
+}
+
+static void cdns_sierra_phy_disable_clocks(struct cdns_sierra_phy *sp)
+{
+ clk_disable_unprepare(sp->pll_cmnlc1);
+ clk_disable_unprepare(sp->pll_cmnlc);
+ clk_disable_unprepare(sp->clk);
+}
+
static int cdns_sierra_phy_get_resets(struct cdns_sierra_phy *sp,
struct device *dev)
{
@@ -961,7 +1013,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
if (ret)
goto unregister_pll_mux;
- ret = clk_prepare_enable(sp->clk);
+ ret = cdns_sierra_phy_enable_clocks(sp);
if (ret)
goto unregister_pll_mux;
@@ -1038,7 +1090,7 @@ static int cdns_sierra_phy_probe(struct platform_device *pdev)
reset_control_put(sp->phys[i].lnk_rst);
of_node_put(child);
clk_disable:
- clk_disable_unprepare(sp->clk);
+ cdns_sierra_phy_disable_clocks(sp);
reset_control_assert(sp->apb_rst);
unregister_pll_mux:
cdns_sierra_pll_mux_unregister(sp, dn);
--
2.17.1
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next prev parent reply other threads:[~2020-12-22 7:12 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-12-22 7:05 [PATCH v2 00/14] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 01/14] phy: cadence: Sierra: Fix PHY power_on sequence Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 02/14] phy: ti: j721e-wiz: Invoke wiz_init() before of_platform_device_create() Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 03/14] dt-bindings: phy: cadence-sierra: Add bindings for the PLLs within SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 04/14] phy: ti: j721e-wiz: Get PHY properties only for "phy" or "link" subnode Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 05/14] phy: cadence: cadence-sierra: Create PHY only for "phy" or "link" sub-nodes Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 06/14] phy: cadence: cadence-sierra: Move all clk_get_*() to a separate function Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 07/14] phy: cadence: cadence-sierra: Move all reset_control_get*() " Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 08/14] phy: cadence: cadence-sierra: Explicitly request exclusive reset control Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 09/14] phy: cadence: sierra: Model reference receiver as clocks (gate clocks) Kishon Vijay Abraham I
2020-12-23 19:00 ` kernel test robot
2020-12-23 22:45 ` kernel test robot
2020-12-22 7:05 ` Kishon Vijay Abraham I [this message]
2020-12-22 7:05 ` [PATCH v2 11/14] arm64: dts: ti: k3-j721e-main: Add DT nodes for clocks within Sierra SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 12/14] arm64: dts: ti: k3-j721e-main: Fix external refclk input to SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 13/14] arm64: dts: ti: k3-j721e-common-proc-board: Use external clock for SERDES Kishon Vijay Abraham I
2020-12-22 7:05 ` [PATCH v2 14/14] arm64: dts: ti: k3-j721e-common-proc-board: Re-name "link" name as "phy" Kishon Vijay Abraham I
2021-01-25 11:31 ` [PATCH v2 00/14] PHY: Add support in Sierra to use external clock Kishon Vijay Abraham I
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