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[84.226.167.205]) by smtp.googlemail.com with ESMTPSA id o74sm3588802wme.36.2020.12.24.04.11.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 24 Dec 2020 04:11:29 -0800 (PST) Date: Thu, 24 Dec 2020 13:11:25 +0100 From: Krzysztof Kozlowski To: Tim Harvey Subject: Re: [PATCH 2/2] arm64: dts: imx8mm: Add Gateworks IMX8MM Development Kits Message-ID: <20201224121125.GC15628@kozik-lap> References: <1608762196-29871-1-git-send-email-tharvey@gateworks.com> <1608762196-29871-2-git-send-email-tharvey@gateworks.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <1608762196-29871-2-git-send-email-tharvey@gateworks.com> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20201224_071131_867141_8AE5E202 X-CRM114-Status: GOOD ( 21.79 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Shawn Guo , Sascha Hauer , linux-kernel@vger.kernel.org, Rob Herring , NXP Linux Team , Pengutronix Kernel Team , Fabio Estevam , linux-arm-kernel@lists.infradead.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Wed, Dec 23, 2020 at 02:23:16PM -0800, Tim Harvey wrote: > The Gateworks Venice GW71xx-0x/GW72xx-0x/GW73xx-0x are development > kits comprised of a GW700x SoM and a Baseboard. > > The GW700x SoM contains: > - IMX8MM SoC > - LPDDR4 DRAM > - eMMC FLASH > - Gateworks System Controller (eeprom/pushbutton/reset/voltage-monitor) > - GbE PHY connected to the IMX8MM FEC > - Power Management IC > > The GW71xx Baseboard contains: > - 1x MiniPCIe Socket with USB2.0, PCIe, and SIM > - 1x RJ45 GbE (IMX8MM FEC) > - PCIe Clock generator > - GPS and accelerometer > - 1x USB 2.0 Front Panel connector > - wide range power supply > > The GW72xx Baseboard contains: > - 2x MiniPCIe Socket with USB2.0, PCIe, and SIM > - 2x RJ45 GbE (IMX8MM FEC and LAN743x) > - 1x MicroSD connector > - 1x USB 2.0 Front Panel connector > - 1x SPI connector > - PCIe Clock generator > - GPS and accelerometer > - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S) > - wide range power supply > > The GW73xx Baseboard contains: > - 3x MiniPCIe Socket with USB2.0, PCIe, and SIM > - 2x RJ45 GbE (IMX8MM FEC and LAN743x) > - 1x MicroSD connector > - 1x USB 2.0 Front Panel connector > - 1x SPI connector > - WiFi/BT > - PCIe Clock generator > - GPS and accelerometer > - Media Expansion connector (MIPI-CSI/MIPI-DSI/GPIO/I2S) > - wide range power supply > > Signed-off-by: Tim Harvey > --- > arch/arm64/boot/dts/freescale/Makefile | 3 + > .../boot/dts/freescale/imx8mm-venice-gw700x.dtsi | 482 +++++++++++++++++++++ > .../boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts | 19 + > .../boot/dts/freescale/imx8mm-venice-gw71xx.dtsi | 186 ++++++++ > .../boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts | 20 + > .../boot/dts/freescale/imx8mm-venice-gw72xx.dtsi | 311 +++++++++++++ > .../boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts | 19 + > .../boot/dts/freescale/imx8mm-venice-gw73xx.dtsi | 363 ++++++++++++++++ > 8 files changed, 1403 insertions(+) > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw700x.dtsi > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx-0x.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx-0x.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw72xx.dtsi > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx-0x.dts > create mode 100644 arch/arm64/boot/dts/freescale/imx8mm-venice-gw73xx.dtsi > > diff --git a/arch/arm64/boot/dts/freescale/Makefile b/arch/arm64/boot/dts/freescale/Makefile > index f8d5943..ecdd233 100644 > --- a/arch/arm64/boot/dts/freescale/Makefile > +++ b/arch/arm64/boot/dts/freescale/Makefile > @@ -32,6 +32,9 @@ dtb-$(CONFIG_ARCH_MXC) += imx8mm-beacon-kit.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mm-var-som-symphony.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw71xx-0x.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw72xx-0x.dtb > +dtb-$(CONFIG_ARCH_MXC) += imx8mm-venice-gw73xx-0x.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-ddr4-evk.dtb > dtb-$(CONFIG_ARCH_MXC) += imx8mn-var-som-symphony.dtb (...) I have few more thoughts below. > diff --git a/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi > new file mode 100644 > index 00000000..a4eeb0d > --- /dev/null > +++ b/arch/arm64/boot/dts/freescale/imx8mm-venice-gw71xx.dtsi > @@ -0,0 +1,186 @@ > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) > +/* > + * Copyright 2020 Gateworks Corporation > + */ > + > +/ { > + aliases { > + usb0 = &usbotg1; > + usb1 = &usbotg2; > + }; > + > + leds { > + compatible = "gpio-leds"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_gpio_leds>; > + > + user1 { /* GRN */ > + label = "user1"; > + gpios = <&gpio5 5 GPIO_ACTIVE_HIGH>; > + default-state = "on"; > + linux,default-trigger = "heartbeat"; > + }; > + > + user2 { /* RED */ > + label = "user2"; > + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; > + default-state = "off"; > + }; > + }; > + > + pps { > + compatible = "pps-gpio"; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_pps>; > + gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>; > + status = "okay"; > + }; > + > + reg_usb_otg1_vbus: regulator-usb-otg1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_reg_usb1_en>; > + compatible = "regulator-fixed"; > + regulator-name = "usb_otg1_vbus"; > + gpio = <&gpio1 12 GPIO_ACTIVE_HIGH>; > + enable-active-high; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + }; > +}; > + > +&ecspi2 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_spi2>; > + cs-gpios = <&gpio5 13 GPIO_ACTIVE_HIGH>; > + status = "okay"; Why is it enabled? What's here? > +}; > + > +&i2c2 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c2>; > + status = "okay"; > + > + accel@19 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_accel>; > + compatible = "st,lis2de12"; > + reg = <0x19>; > + st,drdy-int-pin = <1>; > + interrupt-parent = <&gpio4>; > + interrupts = <5 IRQ_TYPE_LEVEL_LOW>; > + interrupt-names = "INT1"; > + }; > +}; > + > +&i2c3 { > + clock-frequency = <400000>; > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_i2c3>; > + status = "okay"; Why is it enabled? What's here? > +}; > + > +&sai3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_sai3>; > + assigned-clocks = <&clk IMX8MM_CLK_SAI3>; > + assigned-clock-parents = <&clk IMX8MM_AUDIO_PLL1_OUT>; > + assigned-clock-rates = <24576000>; > + status = "okay"; > +}; > + > +&uart1 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart1>; > + status = "okay"; > +}; > + > +&uart3 { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_uart3>; > + status = "okay"; > +}; Why both UARTs are enabled on the Carrier? The console is UART2. Best regards, Krzysztof > + > +&usbotg1 { > + dr_mode = "otg"; > + vbus-supply = <®_usb_otg1_vbus>; > + status = "okay"; > +}; > + > +&usbotg2 { > + dr_mode = "host"; > + status = "okay"; > +}; > + > +&iomuxc { > + pinctrl-names = "default"; > + pinctrl-0 = <&pinctrl_hog>; > + > + pinctrl_hog: hoggrp { > + fsl,pins = < > + MX8MM_IOMUXC_SPDIF_TX_GPIO5_IO3 0x40000041 /* PLUG_TEST */ > + MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6 0x40000041 /* PCI_USBSEL */ > + MX8MM_IOMUXC_SAI1_RXD5_GPIO4_IO7 0x40000041 /* PCIE_WDIS# */ > + MX8MM_IOMUXC_GPIO1_IO07_GPIO1_IO7 0x40000041 /* DIO0 */ > + MX8MM_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x40000041 /* DIO1 */ > + MX8MM_IOMUXC_SAI1_RXD1_GPIO4_IO3 0x40000041 /* DIO2 */ > + MX8MM_IOMUXC_SAI1_RXD2_GPIO4_IO4 0x40000041 /* DIO2 */ > + >; > + }; > + > + pinctrl_accel: accelirq { > + fsl,pins = < > + MX8MM_IOMUXC_SAI1_RXD3_GPIO4_IO5 0x159 > + >; > + }; > + > + pinctrl_gpio_leds: gpioledgrp { > + fsl,pins = < > + MX8MM_IOMUXC_SPDIF_EXT_CLK_GPIO5_IO5 0x19 > + MX8MM_IOMUXC_SPDIF_RX_GPIO5_IO4 0x19 > + >; > + }; > + > + pinctrl_i2c3: i2c3grp { > + fsl,pins = < > + MX8MM_IOMUXC_I2C3_SCL_I2C3_SCL 0x400001c3 > + MX8MM_IOMUXC_I2C3_SDA_I2C3_SDA 0x400001c3 > + >; > + }; > + > + pinctrl_pps: ppsgrp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO15_GPIO1_IO15 0x41 > + >; > + }; > + > + pinctrl_reg_usb1_en: regusb1grp { > + fsl,pins = < > + MX8MM_IOMUXC_GPIO1_IO12_GPIO1_IO12 0x41 > + MX8MM_IOMUXC_GPIO1_IO13_USB1_OTG_OC 0x41 > + >; > + }; > + > + pinctrl_spi2: spi2grp { > + fsl,pins = < > + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 > + MX8MM_IOMUXC_ECSPI2_MOSI_ECSPI2_MOSI 0xd6 > + MX8MM_IOMUXC_ECSPI2_SCLK_ECSPI2_SCLK 0xd6 > + MX8MM_IOMUXC_ECSPI2_SS0_GPIO5_IO13 0xd6 > + >; > + }; > + > + pinctrl_uart1: uart1grp { > + fsl,pins = < > + MX8MM_IOMUXC_UART1_RXD_UART1_DCE_RX 0x140 > + MX8MM_IOMUXC_UART1_TXD_UART1_DCE_TX 0x140 > + >; > + }; > + > + pinctrl_uart3: uart3grp { > + fsl,pins = < > + MX8MM_IOMUXC_UART3_RXD_UART3_DCE_RX 0x140 > + MX8MM_IOMUXC_UART3_TXD_UART3_DCE_TX 0x140 > + >; > + }; > +}; _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel