From: Maxime Ripard <maxime@cerno.tech>
To: Andre Przywara <andre.przywara@arm.com>
Cc: Jernej Skrabec <jernej.skrabec@siol.net>,
Stephen Boyd <sboyd@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
linux-sunxi@googlegroups.com, Chen-Yu Tsai <wens@csie.org>,
linux-clk@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
Icenowy Zheng <icenowy@aosc.io>
Subject: Re: [PATCH] clk: sunxi-ng: h6: Fix CEC clock
Date: Wed, 6 Jan 2021 17:51:36 +0100 [thread overview]
Message-ID: <20210106165136.fx3padj7sdyn7tau@gilmour> (raw)
In-Reply-To: <20210106143246.11255-1-andre.przywara@arm.com>
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On Wed, Jan 06, 2021 at 02:32:46PM +0000, Andre Przywara wrote:
> The CEC clock on the H6 SoC is a bit special, since it uses a fixed
> pre-dividier for one source clock (the PLL), but conveys the other clock
> (32K OSC) directly.
> We are using a fixed predivider array for that, but fail to use the right
> flag to actually activate that.
>
> Fixes: 524353ea480b ("clk: sunxi-ng: add support for the Allwinner H6 CCU")
> Reported-by: Jernej Skrabec <jernej.skrabec@siol.net>
> Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Applied, thanks!
Maxime
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prev parent reply other threads:[~2021-01-06 16:53 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2021-01-06 14:32 [PATCH] clk: sunxi-ng: h6: Fix CEC clock Andre Przywara
2021-01-06 16:06 ` [linux-sunxi] " Chen-Yu Tsai
2021-01-06 16:51 ` Maxime Ripard [this message]
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