Re: [PATCH v3] drm/sun4i: tcon: fix inverted DCLK polarity

Giulio Benetti
2021-01-13T10:50:20Z

On 1/13/21 10:42 AM, Maxime Ripard wrote:
> Hi,
>
> On Mon, Jan 11, 2021 at 06:46:16PM +0100, Giulio Benetti wrote:
>> From: Giulio Benetti <giulio.benetti@micronovasrl.com>
>>
>> During commit 88bc4178568b ("drm: Use new
>> DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
>> macros have been changed to avoid ambiguity but just because of this
>> ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning
>> _SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but
>> instead of swapping phase values, let's adopt an easier approach Maxime
>> suggested:
>> It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to
>> invert DCLK polarity and this makes things really easier than before. So
>> let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_POSITIVE as
>> bit 26 and activating according to bus_flags the same way it is done for
>> all the other signals polarity.
>>
>> Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags")
>> Suggested-by: Maxime Ripard <maxime@cerno.tech>
>> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
>> ---
>> drivers/gpu/drm/sun4i/sun4i_tcon.c | 20 +-------------------
>> drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
>> 2 files changed, 2 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> index eaaf5d70e352..30171ccd87e5 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> @@ -569,26 +569,8 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
>> if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
>> val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
>>
>> - /*
>> - * On A20 and similar SoCs, the only way to achieve Positive Edge
>> - * (Rising Edge), is setting dclk clock phase to 2/3(240°).
>> - * By default TCON works in Negative Edge(Falling Edge),
>> - * this is why phase is set to 0 in that case.
>> - * Unfortunately there's no way to logically invert dclk through
>> - * IO_POL register.
>> - * The only acceptable way to work, triple checked with scope,
>> - * is using clock phase set to 0° for Negative Edge and set to 240°
>> - * for Positive Edge.
>> - * On A33 and similar SoCs there would be a 90° phase option,
>> - * but it divides also dclk by 2.
>> - * Following code is a way to avoid quirks all around TCON
>> - * and DOTCLOCK drivers.
>> - */
>> if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
>> - clk_set_phase(tcon->dclk, 240);
>> -
>> - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
>> - clk_set_phase(tcon->dclk, 0);
>> + val |= SUN4I_TCON0_IO_POL_DCLK_POSITIVE;
>>
>> regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
>> SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
>
> You need to add SUN4I_TCON0_IO_POL_DCLK_POSITIVE to the mask you're
> going to change here too

Ah, lost it during squash, I send a v4.

Thank you
Best regards
--
Giulio Benetti
Benetti Engineering sas