Re: [PATCH v5] drm/sun4i: tcon: fix inverted DCLK polarity

Giulio Benetti
2021-01-14T08:14:19Z

Hi Marjan,

On 1/14/21 8:58 AM, Marjan Pascolo wrote:
> Hi Giulio,
>
> You did a typo
>
> Il 13/01/2021 17:05, Giulio Benetti ha scritto:
>> From: Giulio Benetti <giulio.benetti@micronovasrl.com>
>>
>> During commit 88bc4178568b ("drm: Use new
>> DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags") DRM_BUS_FLAG_*
>> macros have been changed to avoid ambiguity but just because of this
>> ambiguity previous DRM_BUS_FLAG_PIXDATA_(POS/NEG)EDGE were used meaning
>> _SAMPLE_ not _DRIVE_. This leads to DLCK inversion and need to fix but
>> instead of swapping phase values, let's adopt an easier approach Maxime
>> suggested:
>> It turned out that bit 26 of SUN4I_TCON0_IO_POL_REG is dedicated to
>> invert DCLK polarity and this makes things really easier than before. So
>> let's handle DCLK polarity by adding SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE
>> as bit 26 and activating according to bus_flags the same way it is done
>> for all the other signals polarity.
>>
>> Fixes: 88bc4178568b ("drm: Use new DRM_BUS_FLAG_*_(DRIVE|SAMPLE)_(POS|NEG)EDGE flags")
>> Suggested-by: Maxime Ripard <maxime@cerno.tech>
>> Signed-off-by: Giulio Benetti <giulio.benetti@micronovasrl.com>
>> ---
>> V2->V3:
>> - squash 2 patches into 1
>> V3->V4:
>> - add SUN4I_TCON0_IO_POL_DCLK_POSITIVE to regmap_update_bits()
>> V4->V5:
>> polarity is still wrong so:
>> - let's use SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE macro
>> instead of _DCLK_POSITIVE(that would make sense only in realtion with DCLK)
>> - invert condition using _NEGEDGE instead of _POSEDGE and then matching with
>> register bit SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE
>> - correct commit log according to V4->V5 changes
>> ---
>> drivers/gpu/drm/sun4i/sun4i_tcon.c | 21 ++-------------------
>> drivers/gpu/drm/sun4i/sun4i_tcon.h | 1 +
>> 2 files changed, 3 insertions(+), 19 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.c b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> index eaaf5d70e352..c172ccfff7e5 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.c
>> @@ -569,30 +569,13 @@ static void sun4i_tcon0_mode_set_rgb(struct sun4i_tcon *tcon,
>> if (info->bus_flags & DRM_BUS_FLAG_DE_LOW)
>> val |= SUN4I_TCON0_IO_POL_DE_NEGATIVE;
>>
>> - /*
>> - * On A20 and similar SoCs, the only way to achieve Positive Edge
>> - * (Rising Edge), is setting dclk clock phase to 2/3(240°).
>> - * By default TCON works in Negative Edge(Falling Edge),
>> - * this is why phase is set to 0 in that case.
>> - * Unfortunately there's no way to logically invert dclk through
>> - * IO_POL register.
>> - * The only acceptable way to work, triple checked with scope,
>> - * is using clock phase set to 0° for Negative Edge and set to 240°
>> - * for Positive Edge.
>> - * On A33 and similar SoCs there would be a 90° phase option,
>> - * but it divides also dclk by 2.
>> - * Following code is a way to avoid quirks all around TCON
>> - * and DOTCLOCK drivers.
>> - */
>> - if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_POSEDGE)
>> - clk_set_phase(tcon->dclk, 240);
>> -
>> if (info->bus_flags & DRM_BUS_FLAG_PIXDATA_DRIVE_NEGEDGE)
>> - clk_set_phase(tcon->dclk, 0);
>> + val |= SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE;
>>
>> regmap_update_bits(tcon->regs, SUN4I_TCON0_IO_POL_REG,
>> SUN4I_TCON0_IO_POL_HSYNC_POSITIVE |
>> SUN4I_TCON0_IO_POL_VSYNC_POSITIVE |
> Here Below you missed an 'E'

yes, thank you, going to send v6.

Best regards
--
Giulio Benetti
Benetti Engineering sas

>> + SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGDGE |
>> SUN4I_TCON0_IO_POL_DE_NEGATIVE,
>> val);
>>
>> diff --git a/drivers/gpu/drm/sun4i/sun4i_tcon.h b/drivers/gpu/drm/sun4i/sun4i_tcon.h
>> index cfbf4e6c1679..c5ac1b02482c 100644
>> --- a/drivers/gpu/drm/sun4i/sun4i_tcon.h
>> +++ b/drivers/gpu/drm/sun4i/sun4i_tcon.h
>> @@ -113,6 +113,7 @@
>> #define SUN4I_TCON0_IO_POL_REG 0x88
>> #define SUN4I_TCON0_IO_POL_DCLK_PHASE(phase) ((phase & 3) << 28)
>> #define SUN4I_TCON0_IO_POL_DE_NEGATIVE BIT(27)
>> +#define SUN4I_TCON0_IO_POL_DCLK_DRIVE_NEGEDGE BIT(26)
>> #define SUN4I_TCON0_IO_POL_HSYNC_POSITIVE BIT(25)
>> #define SUN4I_TCON0_IO_POL_VSYNC_POSITIVE BIT(24)
>>