From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-14.0 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 4585AC433E0 for ; Thu, 7 Jan 2021 11:17:15 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id E11DF225AC for ; Thu, 7 Jan 2021 11:17:14 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org E11DF225AC Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=9zNKzKRPIKPsJvrcALRlJX5zYEtpFyR35+JfciazVyY=; b=2gTTV8JgVSVgMphTS7VAFLYSC hl7/QzLv/Zwzyuz2hiok6Bzem5ByTC38nNwvIsw6iLIGpuNizZvEpa4AvL3ZeSee5Le4Tt+h8pJzq M16R9qwux9tXwujhk9Nos2BT0+/vNiHcJv+DJtrd5LqOmY4sj9XXSMB9KGUE3H9eodUA+xiar1XvP YLPDYNowxss8hB+vc+nJuiz5pW41LNgBuhza9ii+HGc7u8nhBovWkJbkVdznTsdqkPDwIwrZoirS/ 1daGTb6jRNF6jNuS2RrKwEFd0leaUbOdy3KWwozm+iOHddyTGtf8XADdHZzgWr7AGXQrCD/CyLWWd gceOR2Txg==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxTGV-0000xa-Gn; Thu, 07 Jan 2021 11:15:39 +0000 Received: from foss.arm.com ([217.140.110.172]) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxTGS-0000wl-Pk for linux-arm-kernel@lists.infradead.org; Thu, 07 Jan 2021 11:15:37 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 18C091FB; Thu, 7 Jan 2021 03:15:30 -0800 (PST) Received: from C02TD0UTHF1T.local (unknown [10.57.34.174]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id ACF913F719; Thu, 7 Jan 2021 03:15:27 -0800 (PST) Date: Thu, 7 Jan 2021 11:15:20 +0000 From: Mark Rutland To: Sascha Hauer Subject: Re: [PATCH 1/1] drivers/edac: Add L1 and L2 error detection for A53 and A57 Message-ID: <20210107111520.GA7523@C02TD0UTHF1T.local> References: <20210107103819.13552-1-s.hauer@pengutronix.de> <20210107103819.13552-2-s.hauer@pengutronix.de> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210107103819.13552-2-s.hauer@pengutronix.de> X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210107_061536_894146_2C61D206 X-CRM114-Status: GOOD ( 24.06 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tony Luck , Rob Herring , Robert Richter , James Morse , kernel@pengutronix.de, Borislav Petkov , York Sun , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Sascha, On Thu, Jan 07, 2021 at 11:38:19AM +0100, Sascha Hauer wrote: > The Cortex A53 and A57 cores have error detection capabilities for the > L1/L2 Caches, this patch adds a driver for them. > > Unfortunately there is no robust way to inject errors into the caches, > so this driver doesn't contain any code to actually test it. It has > been tested though with code taken from an older version of this driver > found here: https://lkml.org/lkml/2018/3/14/1203. For reasons stated > in this thread the error injection code is not suitable for mainline, > so it is removed from the driver. > > Signed-off-by: Sascha Hauer > --- > drivers/edac/Kconfig | 6 + > drivers/edac/Makefile | 1 + > drivers/edac/cortex_arm64_l1_l2.c | 218 ++++++++++++++++++++++++++++++ > 3 files changed, 225 insertions(+) > create mode 100644 drivers/edac/cortex_arm64_l1_l2.c [...] > +#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2) > +#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3) Just to note -- these registers are IMPLEMENTATION DEFINED, and so may be trapped by a hypervisor or messed around with arbitrarily by FW. > +static void read_errors(void *data) > +{ > + struct merrsr *merrsr = data; > + > + merrsr->cpumerr = read_sysreg_s(SYS_CPUMERRSR_EL1); > + write_sysreg_s(0, SYS_CPUMERRSR_EL1); > + merrsr->l2merr = read_sysreg_s(SYS_L2MERRSR_EL1); > + write_sysreg_s(0, SYS_L2MERRSR_EL1); > +} ... and so here the MRS instructions may behave as UNDEFINED in some cases. Foer example, KVM would trap these via HCR_EL2.TIDCP, and emulate these as UNDEFINED. > +static const struct of_device_id cortex_arm64_edac_of_match[] = { > + { .compatible = "arm,cortex-a53" }, > + { .compatible = "arm,cortex-a57" }, > + {} > +}; > +MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match); ... and so it's not safe to probe this based on the CPU compatible string alone. If we really need to support this, it will need its own binding (to describe that the reigsters are safe to access and behave in a useful way). Thanks, Mark. _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel