From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-15.5 required=3.0 tests=BAYES_00,DKIMWL_WL_HIGH, DKIM_SIGNED,DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,URIBL_BLOCKED, USER_AGENT_SANE_1 autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 65EFCC433E0 for ; Thu, 7 Jan 2021 12:38:11 +0000 (UTC) Received: from merlin.infradead.org (merlin.infradead.org [205.233.59.134]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id C0F522312A for ; Thu, 7 Jan 2021 12:38:10 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org C0F522312A Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=pengutronix.de Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=merlin.20170209; h=Sender:Content-Transfer-Encoding: Content-Type:Cc:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:References:Message-ID: Subject:To:From:Date:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=vrS1oJuH0enZ+c/JS4E76ibQUVnoeFmWD+PAimGxwP4=; b=tIPFnzQqvwuieKbexk6VdbM5w 3dZTmUzXeHhwHQMDJeXQHmsyWhBGtr9tQTupjfMyzkfnSKVK/6sw3f0QlUjx0b5tDqtT/v3VpZpAw 719D0bVEVGh1erPrAQsi3IzpOkxqNATMtFdNdKs4GtaROgQxfHWxDPphjjY+iJH4EBaTC+08U+wxc 5cBEYBSBOxPm/EzOiaqy8heiAcBhamd2Z9g0LY7lIz/46tz2mJIWT7If1PtGfzW0K15B3u9+Mglhz JeVPzvmi064K1it6iEZISo9Y3TIgtkpMjSKYEnQZ3EBeE3ps0X8BBq2FHerPqFWrlFW9YPaiKQNf5 kJdI5jKIQ==; Received: from localhost ([::1] helo=merlin.infradead.org) by merlin.infradead.org with esmtp (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxUXC-0005uu-FL; Thu, 07 Jan 2021 12:36:58 +0000 Received: from metis.ext.pengutronix.de ([2001:67c:670:201:290:27ff:fe1d:cc33]) by merlin.infradead.org with esmtps (Exim 4.92.3 #3 (Red Hat Linux)) id 1kxUX8-0005tQ-Vl for linux-arm-kernel@lists.infradead.org; Thu, 07 Jan 2021 12:36:56 +0000 Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0]) by metis.ext.pengutronix.de with esmtps (TLS1.3:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.92) (envelope-from ) id 1kxUWq-0006uW-IH; Thu, 07 Jan 2021 13:36:36 +0100 Received: from sha by ptx.hi.pengutronix.de with local (Exim 4.92) (envelope-from ) id 1kxUWm-0001Qr-Dl; Thu, 07 Jan 2021 13:36:32 +0100 Date: Thu, 7 Jan 2021 13:36:32 +0100 From: Sascha Hauer To: Mark Rutland Subject: Re: [PATCH 1/1] drivers/edac: Add L1 and L2 error detection for A53 and A57 Message-ID: <20210107123632.GX19063@pengutronix.de> References: <20210107103819.13552-1-s.hauer@pengutronix.de> <20210107103819.13552-2-s.hauer@pengutronix.de> <20210107111520.GA7523@C02TD0UTHF1T.local> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <20210107111520.GA7523@C02TD0UTHF1T.local> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 13:26:06 up 36 days, 53 min, 73 users, load average: 0.20, 0.09, 0.08 User-Agent: Mutt/1.10.1 (2018-07-13) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: linux-arm-kernel@lists.infradead.org X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20210107_073655_348751_05A0E00E X-CRM114-Status: GOOD ( 32.05 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Tony Luck , Rob Herring , Robert Richter , James Morse , kernel@pengutronix.de, Borislav Petkov , York Sun , Mauro Carvalho Chehab , linux-arm-kernel@lists.infradead.org, linux-edac@vger.kernel.org Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org On Thu, Jan 07, 2021 at 11:15:20AM +0000, Mark Rutland wrote: > Hi Sascha, > > On Thu, Jan 07, 2021 at 11:38:19AM +0100, Sascha Hauer wrote: > > The Cortex A53 and A57 cores have error detection capabilities for the > > L1/L2 Caches, this patch adds a driver for them. > > > > Unfortunately there is no robust way to inject errors into the caches, > > so this driver doesn't contain any code to actually test it. It has > > been tested though with code taken from an older version of this driver > > found here: https://lkml.org/lkml/2018/3/14/1203. For reasons stated > > in this thread the error injection code is not suitable for mainline, > > so it is removed from the driver. > > > > Signed-off-by: Sascha Hauer > > --- > > drivers/edac/Kconfig | 6 + > > drivers/edac/Makefile | 1 + > > drivers/edac/cortex_arm64_l1_l2.c | 218 ++++++++++++++++++++++++++++++ > > 3 files changed, 225 insertions(+) > > create mode 100644 drivers/edac/cortex_arm64_l1_l2.c > > [...] > > > +#define SYS_CPUMERRSR_EL1 sys_reg(3, 1, 15, 2, 2) > > +#define SYS_L2MERRSR_EL1 sys_reg(3, 1, 15, 2, 3) > > Just to note -- these registers are IMPLEMENTATION DEFINED, and so may > be trapped by a hypervisor or messed around with arbitrarily by FW. > > > +static void read_errors(void *data) > > +{ > > + struct merrsr *merrsr = data; > > + > > + merrsr->cpumerr = read_sysreg_s(SYS_CPUMERRSR_EL1); > > + write_sysreg_s(0, SYS_CPUMERRSR_EL1); > > + merrsr->l2merr = read_sysreg_s(SYS_L2MERRSR_EL1); > > + write_sysreg_s(0, SYS_L2MERRSR_EL1); > > +} > > ... and so here the MRS instructions may behave as UNDEFINED in some > cases. Foer example, KVM would trap these via HCR_EL2.TIDCP, and emulate > these as UNDEFINED. > > > +static const struct of_device_id cortex_arm64_edac_of_match[] = { > > + { .compatible = "arm,cortex-a53" }, > > + { .compatible = "arm,cortex-a57" }, > > + {} > > +}; > > +MODULE_DEVICE_TABLE(of, cortex_arm64_edac_of_match); > > ... and so it's not safe to probe this based on the CPU compatible > string alone. If we really need to support this, it will need its own > binding (to describe that the reigsters are safe to access and behave in > a useful way). Rob objected to adding dedicated nodes to attach the driver to. That leaves adding a property like "edac-enabled" or similar to the CPU nodes when edac is desired. Would that be ok? Sascha -- Pengutronix e.K. | | Steuerwalder Str. 21 | http://www.pengutronix.de/ | 31137 Hildesheim, Germany | Phone: +49-5121-206917-0 | Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 | _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel